Communications

Gigabit Ethernet TCP/IP offload engine module

13th November 2013
Nat Bowers

Orange Tree Technologies has today introduced a new high performance Gigabit Ethernet TCP/IP offload engine module, the ZestETM1. Measuring just 25 mm x 30mm, the ZestETM1 provides a simple ready-to-go high speed Ethernet data interface solution, saving developers the headache of getting to grips with the complexity of TCP/IP or creating their own Ethernet interface.

Matt Bowen, Software Director at Orange Tree, commented: "We based the design of GigExpedite on the TCP/IP engine of our highly successful current product ZestET1. This was following feedback from customers who wanted to use their own embedded processor instead of the FPGA on ZestET1. The new product design has therefore been shaped by over 4 years’ practical user experience."

Enabling maximum efficiency with the user's embedded processor or FPGA to be dedicated entirely to the application, the proprietary protocol chip GigExpedite handles the whole TCP/IP stack at over 100MBytes/sec in each direction. Since the TCP/IP consumes considerable processing power at Gigabit speed, the embedded processor or FPGA is freed up for the application’s function using a separate dedicated TCP/IP engine.

The highly adaptable ZestETM1 interface can be configured to one of four modes: 8 or 16-bit SRAM-style bus, FIFO, or 'bit banging': the SRAM-style bus modes are similar to an SRAM interface with the application writing and reading ZestETM1; the FIFO mode has two separate 8-bit channels streaming in each direction to and from ZestETM1; and the innovative 'bit-banging' mode enables another device on the network to write or read up to 32-bit values to or from an attached device.

"With the increasing use of Ethernet in many different markets such as industrial control, machine vision, defence and the medical sector, the ZestETM1 can speed the time to market for many companies, creating a key advantage for them, " comments Charles Sweeney, Hardware Director at Orange Tree.

Configurable as either an SPI slave or a UART, a low speed serial interface allows a low performance processor to control ZestETM1 while the high speed data interface is connected to the application data path such as FPGA, ADC, DAC or bus transceivers. A separate SPI master interface can be used for mulitple applications, such as to configure an attached FPGA or processor.

Running at 10/100/1000 MBits/sec and delivering over 100MBytes/sec sustained in each direction, the TCP/IP engine in GigExpedite implements TCP/IP, UDP, ARP, IPv4, ICMP, IGMP, PTP and HTTP protocols. Time of day and a 125MHz clock synchronised across the network are offered by Precision Time Protocol and SyncE for real-time applications.

Featured products

Product Spotlight

Upcoming Events

View all events
Newsletter
Latest global electronics news
© Copyright 2021 Electronic Specifier