CPU IP cores combine virtualisation and scalable performance

According to IMG, the family achieves over 50% higher CoreMark performance and 30% higher DMIPS when compared to competitors. The family of cores, which are also claimed to achieve high frequencies in aggressive implementations, can be implemented across a very wide range of performance, power and area operating points. 

Featuring hardware multi-threading technology, the I6400 family supports up to four hardware threads per core. With the technology, the execution of multiple instructions from multiple threads is enabled during every clock cycle. Preliminary benchmarking shows that adding a second thread leads to performance increases of 40-50% on industry benchmarks such as SPECint and EEMBC’s CoreMark, with less than a 10% cluster area increase. 

The family incorporates hardware virtualisation technology, providing increased security and reliability and support for up to 15 secure/non-secure guests. To address the privacy and security needs of evolving and emerging connected applications, the family of cores are optimised to support multiple independent security contexts and multiple independent execution domains. The I6400 family scales to support secure content delivery, secure payments, identity protection and more across multiple applications and content sources. 

With PowerGearing, the family features advanced power management capabilities. This includes the ability to provide a dedicated clock and voltage level to each core in a heterogeneous cluster, while maintaining coherency across CPUs so that sleeping cores only need to wake when needed. A Floating Point Unit (FPU) is featured within the family of cores, supporting both single and double precision capabilities relevant to general computing and improved control systems processing.

Featuring 128-bit SIMD support, the I6400 family delivers high performance and high throughput for a wide range of tasks. The support is built on the MIPS SIMD architecture, with instructions defined to be easily supported within high-level languages such as C or OpenCL. Supporting a wide variety of integer (8, 16, 32 and 64-bit) and floating point (32 and 64-bit) data types, the SIMD is efficient for many applications across audio, video, vision, and other computationally-intensive use cases.

Featuring the latest generation of the MIPS Coherency Manager fabric, the family supports multicore configurations of up to six cores per cluster. With this, multiple cores on a single cluster can have different synthesis targets and operate at different clock frequencies and voltages. The Coherency Manager fabric also implements hardware pre-fetching along with buses and latencies which are wider and lower than previous generations.

Supporting multi-cluster fabric configurations up to 64 clusters, the family is designed to be delivered in diverse combinations of threads, cores and clusters. The family of cores are also designed to operate in heterogeneous clusters in future SoC implementations leveraging CPUs, GPUs and other processing elements.

Based on the MIPS Release 6 (r6) architecture, the I6400 family benefits from the MIPS instruction set. Targeting next-generation applications, MIPS r6 features new instructions for enhanced performance on JITs, JavaScript, browsers, PIC (position independent code) for Android, and today’s larger workloads. This architecture does not require separate ISAs, datapaths or mode switching, eliminating wasted silicon area and power. 

I6400 customers benefit from the broad ecosystem that already exists around MIPS, including software, tools and applications and the new prpl open source foundation. With founders Broadcom, Cavium, Ikanos, Ineda Systems, Ingenic Semiconductor, Lantiq, PMC, Qualcomm Incorporated and others, prpl is delivering open source software for MIPS I-class and other Warrior cores with a focus on markets from IoT to datacenter.

A broad range of development tools and software is already available or in development for the I6400 cores, from IMG and other companies across the MIPS ecosystem. Hypervisors are in development for the family, enabling customers to take advantage of hardware virtualisation and enhanced multi-context security capabilities.

One of the first projects completed through the prpl open source foundation is support for the MIPS64 r6 architecture in the QEMU open source emulator. With QEMU, developers can get started on developing applications and software for the I6400 family. The family of cores are suitable for embedded, mobile, digital consumer, advanced communications, networking and storage applications. General availability is scheduled for December 2014.

Tony King-Smith, EVP marketing, Imagination, says: “This is the MIPS Warrior core that many have been waiting for. As the industry moves toward instruction set neutrality, customers can now choose a CPU based on its technical superiority. The I6400 is more efficient, flexible and scalable than the competition, and its feature set clearly lends itself to the needs of a wide range of next-generation applications including smartphones and tablets. We know that unique features like multi-threading provide significant advantages for many applications, and customers already using this technology agree. Unsurprisingly, we’ve already secured licensees for the I6400 across multiple markets.”

Jim McGregor, Founder and Principal Analyst, Tirias Research, says: “To address the ongoing evolution in applications from IoT to mobile to networking and storage, companies need to select scalable platforms that can future-proof their designs. With 64-bit, multi-threading, and multicore/multi-cluster support, the I6400 is designed to be a phenomenally flexible, low-power processor architecture capable of scaling across a wide range of applications. Imagination now has MIPS IP cores for everything from microcontrollers to 64-bit servers, delivering choice across the range and changing the competitive dynamic in the industry.”