Communications

Analog Devices announces RadioVerse SoC series

13th December 2021
Kiera Sowery

Analog Devices announces its RadioVerse SoC (system-on-chip) series providing radio unit (RU) developers with an agile and cost-effective platform to create energy efficient 5G RUs.

The SoC series provides RF signal processing with expanded digital functionality and RF capacity that greatly improves 5G RU performance and energy efficiency. The SoCs are the newest addition to ADI’s RadioVerse ecosystem and combine its Zero IF (ZiF) architecture with advances in functional integration and linearisation.

“Samsung and ADI have long worked together to support the swift deployment of 5G in the global market,” said Dong Geun Lee, Vice President and Head of Hardware R&D Group, Network Business at Samsung Electronics. “We are excited for the successful launch of ADI’s new SoC, as we expect this cutting-edge technology will bring better 5G experience to consumers. We look forward to expanding our engagement with ADI.”

Demand for power efficient RUs is expanding rapidly as global network operators race to deploy 5G infrastructure. With the exponential growth of wireless demand, energy efficiency is a key metric for operators as they seek to reduce their carbon footprint while expanding network capacity. The RadioVerse SoC series requires low power compared to alternatives and implements advanced algorithms that deliver optimal RU system efficiency.  

“RadioVerse SoCs are designed to optimise the full radio solution rather than just a single component or interface,” said Joe Barry, Vice President of Wireless Communications at Analog Devices. “Each successive generation has provided expanded capabilities, bandwidth and performance, while improving overall RU efficiency. This new RadioVerse SoC series takes a big step forward by delivering multiple advancements in signal processing to meet the demanding needs of 5G.”

The ADRV9040 is the first in the RadioVerse SoC series. It offers eight transmit and receive channels of 400MHz bandwidth and integrates advanced digital signal processing functions, including carrier digital up-converters (CDUC), carrier digital down-converters (CDDC), crest factor reduction (CFR) and digital pre-distortion (DPD).

This expanded signal processing can eliminate the need for a field-programmable gate array (FPGA), thereby reducing thermal footprint, and total system size, weight, power, and cost. The SoC’s DPD algorithms were developed using advanced machine learning techniques and are optimised in close collaboration with major power amplifier (PA) vendors to ease the design burden and deliver bandwidth performance.

The algorithms are fully tested and validated across 4G and 5G use cases, including various PA technology types such as gallium nitride (GaN). In addition, the ZiF radio architecture simplifies RF filtering and signal chain components, reducing RU cost and development time for band and power variants designs.

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