56Gb/s SerDes targets next-gen switches & routers

PAM4 technology enables future scaling of core/metro router and hyperscale data centres by more than doubling link throughput to 56Gb/s from 25Gb/s, in full duplex per differential pair. Rack-level applications will particularly benefit from PAM4 technology realising advantages in space, power, cost, and simplified cabling.

The Avago 56Gb/s PAM4 SerDes is designed to support a wide range of copper and optical interconnects ranging from chip-to-chip, chip-to-module, low-cost direct-attached cable, and copper backplane down to 35dB loss. The SerDes supports speeds from 1 to 56Gb/s, including existing 10G/25G/40G/50G/100G Ethernet, Fibre Channel, and OIF CEI NRZ speeds, providing a forward-looking architecture path to networking, compute system vendors, and mega data centre companies.

By also targeting emerging OIF CEI-56G-VSR and IEEE 802.3bs (400GE) electrical standards defining next-gen chip-to-module interconnect, the Avago 56Gb/s PAM4 SerDes provides the additional benefit of enabling the same PAM4 signaling deployment on front side and back side interfaces, thus increasing SoC use case flexibility and reusability across hardware platforms.

The Avago 56Gb/s PAM4 SerDes is running PRBS31 traffic, error-free, across various interconnects up to 56Gb/s, thus reducing ASIC development risk and accelerating Avago customer system deployment.

“Avago is proud to deliver the PAM4 56Gb/s SerDes that ushers in an era of SerDes interconnect technology for networking applications,” said Frank Ostojic, Senior Vice President and General Manager, ASIC Products Division, Avago. “Our customers are utilising the PAM4 SerDes cores to design ASIC solutions to meet the explosive bandwidth growth in datacentre and service provider networks.”