Tessent safety ecosystem helps AI vision processor

“Design-for-Test (DFT) is a critical element of integrated circuit (IC) design, especially for cutting-edge AI devices targeting safety-critical automotive applications,” said Praveen Jaini, Director of VLSI for Ambarella. “Mentor’s Tessent Safety ecosystem offered us a vast array of powerful, time-saving features that helped us to achieve our design goals quickly, with cost-efficiency and with the reliability that our customers have come to expect. Because Mentor’s Tessent ecosystem is highly scalable, it provides optimal flexibility for developing alternative designs and next-generation devices.”

Encompassing a broad spectrum of Mentor IC test technologies, the Tessent Safety ecosystem is a comprehensive portfolio of best-in-class automotive IC test solutions with links to Mentor’s industry-leading partners. The ecosystem delivers a range of advanced IC test technologies, including in-line device monitoring – an innovative approach that distributes embedded monitors throughout each semiconductor device, all connected through a common infrastructure to enable rapid detection and reporting of random failures anywhere in the system.

“The prospect of near-term automated driving presents the semiconductor industry with tremendous opportunity, while presenting a host of new technology challenges,” said Brady Benware, Vice President and General Manager for the Tessent product family at Mentor, a Siemens business. “The Tessent Safety ecosystem helps our customers tackle and overcome these challenges with a scalable DFT architecture specifically engineered to address the intense time, cost and quality requirements associated with autonomous vehicle IC design.”

The design for Ambarella’s CV22FS and CV2FS SoCs utilised the following Tessent Safety ecosystem technologies:

• Tessent LogicBIST software, which is the industry’s leading built-in self-test solution for testing the digital logic components of integrated circuits. It includes unique features targeted at nanometer SoC designs that reduce test costs and shorten time-to-market, while maximising test quality.
• Tessent MemoryBIST platform, which features a comprehensive automation flow that provides design rule checking, test planning, integration, and verification at either the RTL or gate level.
• The Tessent MissionMode product, which provides a combination of automation and on-chip IP for enabling semiconductor chips throughout an automotive electronics system to be tested and diagnosed at any point during a vehicle’s functional operation.