The ‘intelligence revolution’ in computing is no longer about bolting on one more accelerator or building a bigger server; it is about keeping clusters of GPUs, CPUs, and DPUs fed at line rate.
The new limit in AI infrastructure is not raw compute, but the risk of starving expensive accelerators because the I/O fabric cannot move data fast enough. PCIe 4.0 – and increasingly even Gen5 – has become the bottleneck, and that pushes PCIe Gen6 and the growing CXL ecosystem from ‘next standard on the roadmap’ to the fabric on which AI-native systems will run.
At its core, this is an architectural reset. The centre of gravity is moving away from a single CPU-centric motherboard view towards distributed, fabric-native designs: chassis full of accelerators, disaggregated memory pools, and SmartNICs and DPUs that take on more of the I/O, storage, networking and security work. Coherent interconnects like CXL allow such systems to link memory and accelerators in ways that blur the line between ‘local’ and ‘remote’ resources and make bandwidth a key design parameter rather than hidden plumbing.
PCIe Gen6: doubling throughput, changing assumptions
PCIe has long been the main interconnect in servers, networking gear and storage, but Gen 6.0 is not ‘just’ a speed bump. It doubles the raw bit rate to 64 GT/s per lane using PAM4 signalling, introduces FLIT-based packet framing, and adds low-latency FEC so that the physical layer can be pushed harder without sacrificing link reliability. For AI and HPC designers, these are not simple checklist features; they enable new system designs: wider pipes per slot, denser fan-out through PCIe switches, and topologies that go beyond a single root complex.
At hyperscale, these technical details turn directly into business drivers. Doubling effective bandwidth while keeping latency under control means more training jobs per rack, higher utilisation of deployed accelerators, and better ROI on AI infrastructure investments. Importantly, the impact is not limited to large training clusters. Inference-heavy Edge and telco environments also benefit as PCIe Gen6-capable FPGAs and SmartNICs offload, inspect and accelerate mixed workloads at the network and storage Edge.
Why soft PCIe IP on FPGAs matters
In this context, soft PCIe IP on FPGAs moves from niche to central. In domains where ASIC hard IP once dominated completely, we now see a shift back to FPGA-based solutions for several reasons:
Pace of change. AI-native workloads and interconnect standards are both changing. Waiting multiple years for an ASIC refresh is no longer acceptable when system vendors need to respond to a changing mix of GPUs, NPUs, storage tiers and network fabrics. Soft IP lets the interconnect evolve at the pace of software releases, not silicon spins.
Customisation and differentiation. FPGAs allow vendors to tailor PCIe endpoints, switches and bridges for very specific behaviours – protocol testers and exercisers, inline security and encryption, traffic shaping, or ultra-low-latency network appliances. Differentiation more and more lives in this last programmable layer above the hard PHY.
Integration and observability. Soft IP in an FPGA does not live alone. It sits alongside packet inspection, compression, telemetry and timing logic that allows OEMs to see and shape traffic in ways that hard IP blocks cannot easily expose, and to prove those behaviours with lab results and debug hooks.
From an architecture point of view, this is not a return to the ‘old FPGA’ era, where programmable fabric was used only for glue logic or narrow offloads. With Gen6-class soft controllers, FPGAs become a programmable data plane: making routing decisions, enforcing QoS, coordinating data movement between GPU clusters, NVMe storage and SmartNIC-based accelerators, and providing the evidence that these systems behave as promised.
CXL: from buzzword to practical fabric
In parallel, the CXL ecosystem is maturing from slide decks into shipping products. CXL 3.0 extends the original cache-coherent model into a flexible fabric that supports device-to-device communication, pooled memory and scalable switching topologies. For AI and data-intensive workloads, this turns memory from a rigid, on-board resource into something that can be assembled and rebalanced as the workload mix changes.
For FPGA and system designers, the meeting point of PCIe Gen6 and CXL is where some of the most important innovations will happen. PCIe 6.0 remains the underlying physical layer; CXL rides on top to provide coherence and logical fabric services. Soft IP cores that are directly aware of both standards let vendors prototype and deploy CXL-capable solutions without waiting for an entire ASIC generation to catch up, and without trapping themselves in a single fixed topology.
India’s opportunity: build the boards and IP that feed global AI
For countries like India, the intelligence revolution is not only about deploying AI applications; it is about building the compute infrastructure that trains and serves them. PCIe Gen6 controllers, CXL bridges and related IP blocks running on FPGAs are a chance to move up the value chain – from assembling servers to designing the high-speed data paths and reference platforms that define their performance.
Companies that can offer silicon-proven, compliance-tested soft IP together with system-level design, verification and bring-up expertise will be well placed to serve both global chip vendors and Indian OEMs. That means not only providing IP blocks, but also full reference designs, test suites, and field engineering support that cut time-to-revenue for every new AI or HPC platform and make interconnect behaviour something customers can inspect and trust, not just assume.
The intelligence revolution runs on bandwidth. PCIe Gen6 and CXL are changing how that bandwidth is delivered and used. The next wave of growth will belong to those who treat interconnects as a strategic lever for AI-native systems – and who can ship the programmable IP, boards and proof that make that lever real.
About the author:
Sunil Kar, President & CEO, Logic Fruit Technologies
Sunil Kar is a US-based semiconductor executive with over 30 years of experience driving business growth, innovation, and global operations. He has held senior leadership roles including Vice President and Business Head at Xilinx (acquired by AMD), General Manager at IDT (acquired by Renesas), SVP at Ascenium, and senior positions at NetLogic (acquired by Broadcom) and NEC (Japan). He began his career with Analog Devices and has led global cross-functional teams, managed businesses exceeding $500 million in annual revenue, and driven multiple M&A and strategic partnership initiatives. Sunil also advises both startup and public semiconductor companies, leveraging deep domain expertise across data centre/computing, mobile telecom, and enterprise market segments.
