IMVP-6/6+/6.5 Single-Phase DC/DC Controller

21st July 2010

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Datasheet

Linear Technology introduces the LTC3816, a single-phase synchronous step-down DC/DC controller implementing the Intel® IMVP-6®, IMVP-6+®, and IMVP-6.5® protocols. Intel Mobile Voltage Positioning (IMVP) is a smart voltage regulation technology that effectively reduces the amount of output capacitance required for a given output error budget. On-chip support is provided for all the IMVP-6/6+/6.5 requirements, including a 7-bit VID code, start-up to a preset boot voltage (VBOOT), differential remote output voltage sensing, programmable active voltage positioning (AVP), output current reporting (IMON, IMVP-6.5) and power optimization during deeper sleep state to increase the battery run time.

The LTC3816 incorporates a parallel input, 7-bit digital-to-analog converter (DAC), which dynamically adjusts its output to the Intel CPU core supply voltage from 0V to 1.500V in 12.5mV steps with +0.75% VOUT accuracy over temperature. It operates from an input voltage ranging from 4.5V to 36V, has powerful onboard N-channel MOSFET gate drivers and can control output currents up to 25A. Its leading edge modulation architecture enables a very low output voltage to be regulated from a high input voltage and still operates at high frequency (phase-lockable up to 550kHz). A unity-gain differential amplifier provides remote voltage sensing at the CPU, eliminating errors due to parasitic IR drops across PCB metal traces.

Current sensing can be implemented with either a temperature-compensated lossless inductor DCR network, or with a discrete sense resistor. If DCR sensing is used, an NTC thermistor network will compensate for the gain and time constant variations caused by the inductor DCR temperature coefficient.

The LTC3816 can operate in pulse-skipping or forced continuous mode. Pulse skipping provides the highest light load efficiency, while forced continuous operation has faster transient response at light load. AVP minimizes the peak-to-peak output voltage transient during a step load.