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Taking Multicore to the Next Level: KeyStone II Architecture

10th April 2015
Nat Bowers
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TI’s scalable KeyStone II multicore architecture includes support for both TMS320C66x DSP cores and multiple cache coherent quad ARM Cortex-A15 clusters, for a mixture of up to 32 DSP and RISC cores. With significant updates to its award-winning KeyStone architecture, TI is now paving the way for a new era of high performance 28-nm devices that meld signal processing, networking, security and control functionality, with KeyStone II.

Ideal for applications that demand superior performance and low power, devices based on the KeyStone architecture are optimised for high performance markets including communications infrastructure, mission critical, test and automation, medical imaging and high performance and cloud computing. For more information, please visit www.ti.com/multicore.

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