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How to make the best use of SoC FPGAs in new designs

7th January 2014
Nat Bowers

Engineers can find it challenging to design systems based round FPGAs with integrated ARM processors. At the National Electronics Week (held at the NEC in Birmingham from 8 to 10 April 2014), the basics will be explained in depth at this year’s Embedded Masterclass.

A dedicated engineering design conference for the embedded community, UMR’s Embedded Masterclass will run concurrently to the National Electronics Week exhibition. Altera's Stefano Zammattio will explain how combining the two technologies on one die has enabled a level of integration that was not possible in discrete device packages.

Explaining how to move from designing with a single-core provcessor to one using two or more cores, Zammattio will explore the issues that occur when designing with dual-core processors (focusing on AMP and real-time systems) as well as offering advice on how to design high-performance SoC FPGA systems.

Zammattio comments: “This brings higher performance and capabilities that were not possible before. As these capabilities were not possible previously, developers have little experience of the issues that can arise and can easily develop sub-optimal systems.”

By bringing together the Embedded Masterclass and National Electronics Week, delegates can make more efficient use of their time away from the office. Offering an opportunity to learn and engage with key industry experts in one arena, the ition will have a focused Embedded Zone featuring the best in the industry. Seminars and workshop theatres will be integrated into this area to allow delegates plenty of time to engage with suppliers, view demo areas and discuss industry issues in one location.

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