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Digital design solutions centre stage at DesignCon 2021

At DesignCon 2021in the San Jose McEnery Convention Center (August 16-18) Keysight Technologies’ technical experts will highlight high-speed digital designs across all product development stages.

These enable customers to anticipate test challenges and optimise performance, as well as accelerate time-to-market of high-speed computing interfaces, data centre connections and consumer electronics.  

Keysight will deliver the following demonstrations that help accelerate a customer's digital designs:  

  • PathWave Design
    • PathWave Advanced Design System (ADS) and workflow wizards to reduce design iterations in next-generation memory system designs. 
  • High-Speed Computing Interfaces
    • PCI Express (PCIe) transmitter (Tx) and receiver (Rx) test solutions (PCIe5 and PCI6 pathfinding) that examine signal integrity challenges, issues with connector crosstalk, receiver jitter sensitivity, overall channel insertion loss and attenuated signals.
    • Input/output buffer information specific (IBIS) algorithmic modelling interface (AMI) models on an enhanced double data rate (DDR5) bit-by-bit channel simulator that provides signal access, automated control of the device under test (DUT) for fast repeatable test and a data repository for quick result analysis and rapid decision making.
  • Data Centre Connectivity
    • An automated test system for 100 Gbps physical layer (PHY) validation (800G) which requires unique, precision measurements to validate new test methods and specifications before the standard is complete.
    • A compliance test solution for 400GBASE devices and components to achieve increased bandwidth in data centre networks and designed to integrate forward error correction (FEC) constraints into the physical design validation.
  • Consumer Electronics
    • USB4 and DisplayPort 2.0 compliant solutions over a lossy (using inexact approximations and partial data discarding to represent content), low cost, passive cable with Keysight's UXR-Series oscilloscope (pictured).
  • Signal Integrity
    • Offering insight into associated signal integrity challenges such as reflections, eye diagram closure, crosstalk, and bit errors at the receiver for up to 800G physical layer interconnect components.
  • Intelligent Software Test Automation
    • How to enable companies to view their technology through the eyes of their users to identify and address interface errors and performance issues before they go into production. 

In Executive Ballroom Room 210E, Keysight's test and measurement experts will offer complimentary Keysight Education Forum (KEF) sessions:

Tuesday, August 17th Sessions

  • Advanced Testing Challenges at 32GBaud PAM4 with PCIe 6.0
  • Next Gen Development in Type-C Ecosystem
  • Physical Layer Validation Challenges of Characterizing 100 Gbps/lane Designs
  • Solving Forward Error Correction Problems

Wednesday, August 18th Sessions

  • Guide to Recalibrate Signal Integrity Intuition for Memory Interfaces
  • Ramping up on the Latest Skills for Power Integrity Design/Debug
  • Next-Generation Memory Solutions
  • Explore Why Testing Disaggregated 5G Elements in Isolations is Required to Ensure Proper O-RAN Fronthaul Conformance

In addition, on Tuesday, August 17, visit the Chiphead Theatre from 2:15 to 3:00 p.m. Keysight will host the Modernisation of Test and Measurement technical session.

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