At embedded world 2026, on the DigiKey booth, Paige Hookway speaks with Miha Gjura, Field Application Engineer at Red Pitaya, about new ways for multichannel synchronisation.
For those unfamiliar with Red Pitaya, the company builds compact, open-source hardware solutions that combine an FPGA development platform with a small form factor Linux computer and a web-based instrument interface — all designed to help customers accelerate their time to market. It’s a versatile platform that has accumulated an impressive range of use cases across research, testing, and embedded development.
The journey toward sophisticated multi-channel synchronisation began with the classic STEMlab 125-14, a board offering two RF input and two RF output channels. Over time, Red Pitaya introduced a four-input variant, followed by the X-channel system — a daisy-chain architecture that allowed multiple boards to be synchronised via clock and trigger signals. Now, the Gen 2 platform takes that concept further with the introduction of click shields.
“The second generation of the X-channel system is done via the click shields,” Gjura explained, noting that the new approach supports both external clock and external trigger inputs, moving beyond the internal master trigger of the previous generation. Critically, the click shields employ shared clock buffers distributed across multiple boards, enabling what Gjura describes as “flawless synchronisation.” The system is also highly scalable — users can mix and match board variants, combining, for example, a four-input board with a two-in/two-out board to achieve a six-input, two-output configuration, with the architecture expandable almost indefinitely.
One of the most significant technical advances showcased at the event was a dramatic increase in streaming speeds, jumping from 20 to 62.5 megabits per second. Gjura was candid that the achievement, while sounding deceptively simple, required substantial engineering effort. “It was mostly redesigning a bit of the FPGA and then rewriting, optimising the code,” he said, adding that the platform is now approaching the hardware limits of the Zynq 7010 and 7020 chips at the heart of the boards.
This boost in throughput unlocks meaningful new workflows. Building on the deep memory acquisition feature introduced previously — which enabled streaming data from inputs to onboard RAM — the Gen 2 platform now supports the reverse process. Users can pre-record or capture longer data sequences and then replay them through the board’s outputs, opening up new possibilities for test and simulation scenarios.
Managing multi-board systems has also been simplified. New boards can switch between internal and external clock sources via a single GPIO pin, and connecting additional boards is as straightforward as attaching a click shield and linking the boards with U.FL cables. Software control is handled through SCPI commands or a custom streaming client that enables simultaneous control of all connected boards, with the ability to both receive and generate data across the full system.
With Edge AI dominating the conversation at this year’s show, Gjura acknowledged that the pace of innovation is relentless. Red Pitaya’s expanded synchronisation and streaming capabilities position the platform well for the data-intensive, multi-channel acquisition and generation tasks that are increasingly central to modern embedded and instrumentation applications. “This is a future that customers are really going to be able to utilise,” says Gjura.
Watch the full conversation here.
