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Baya Systems takes wraps off IP for chiplet design

24th June 2024
Mick Elliott

Start-up Baya Systems has emerged from stealth mode to announce its software-driven IP technology portfolio designed to accelerate complex single-die and multi-die SoC designs.

The company says that these innovations bolster the emerging chiplet economy and enable unprecedented scale for large-scale compute and AI processing.

Baya Systems technology simplifies the development process and reduces the risk, empowering designers to rapidly analyse, develop, optimise and deploy these complex systems.

This enables highly energy-efficient data movement in single-die designs that can support over 4 terabyte/second throughput in a complex CPU cluster, culminating in multi-petabyte/second throughput in multi-chiplet designs for high-end AI installations.

With the exponential growth of computing requirements for artificial intelligence, best-in-class silicon vendors have consistently tried to scale performance efficiently by integrating various processors, including CPUs, GPUs, and neural network accelerators, into intelligent compute systems.

This has led to a substantial challenge of efficient data movement across these different processors, and increasingly complex system and application software development.

Baya Systems focuses on delivering hyper-efficient data movement that can be customized with efficient hardware-based coherency, correctness, and robustness to accelerate these platforms for applications across industries such as AI acceleration, data centre, networking infrastructure, automotive and IoT.

“The rapid scaling in compute needed to support AI is bottlenecked by scaling silicon, memory, storage, and the increasingly huge amounts of data; requiring increasingly complex SoCs and chiplets,” said Kevin Krewell, Principal Analyst at TIRIAS Research. “The industry desperately needs a holistic way to design, analyse, and build intelligent fabrics to address this, and Baya seems to have the right ingredients to really drive the market forward.”

Baya Systems tackles the challenges of system design complexity, performance guarantees, high costs, and shrinking market windows in the SoC and chiplet industries. Its WeaverPro software platform supports the SoC designer from initial specification all the way to post-silicon tuning.

Its WeaveIP provides components to build a unified fabric that has an extremely efficient, scalable transport architecture that maximises performance and throughput, while minimizing latency, silicon footprint and power.

Combined with advanced features for reliability and safety, this empowers designers to analyse, architect, customise, optimize and deploy complex SoCs and chiplets.


Baya says its solution is unique for the following reasons:

  • Software-driven architecture exploration helps optimize design to achieve performance guarantees based on built-simulator.
  • Engine to generate representative workloads from traffic specification.
  • Best-in-class, flexible network that can achieve 3GHz in a 4-nanometer process technology.
  • Algorithmic optimisation that supports reuse and minimizes silicon and power footprints without compromising performance.
  • Industry’s first IP to offer multi-level cache coherency for single/multi-die systems, radically reducing costs of coherency across these large-scale systems.
  • Customisable protocol and multicast capabilities for advanced AI and CPU acceleration that support petabyte-level throughput.
  • Correct-by-construction design generation that radically reduces risk of failure.
  • WeaveIP supports standard protocols such as CHI, ACE5-Lite, AXI5 and extendable to others including CXL.
  • Physically aware flow with modularity and tiling support for ease of implementation


“The semiconductor industry is at an inflection point in how to overcome the widening gap between memory performance and the processing needs of AI,” said Dr. Sailesh Kumar, CEO at Baya Systems. “These challenges are overwhelming the industry with design complexity, energy costs, and systems that are obsolete by the time they hit the market. Baya Systems is resolute in delivering foundational software, an industry-first, grounds-up fabric solution for future-proof multi-cluster and multi-chiplet designs, and a methodology that takes out the guesswork. I firmly believe that Baya unlocks the merchant chiplet market that is expected to grow to $107 billion by 2033.”


Baya Systems was founded by Kumar, an ex-Intel Fellow and former founder of Netspeed Systems; Dr. Eric Norige, and Joji Philip, who were also key contributors at Netspeed Systems.

It is backed by leading investors Matrix and Intel Capital, and is led by Silicon Valley semiconductor veterans with extensive experience in processing and systems, who have driven important initiatives at AMD, ARM, Apple, Intel, Meta, and other leading processor companies.


“When we invest, we look for key market gaps, disruptive technologies that address them, and teams that have a compelling vision and execution muscle and the hunger to achieve it,” said Stan Reiss, general partner, Matrix Partners. “Baya tops all of them for a market that is desperate for solving the scale and chiplet problem with a technology that not just fills the gap but unleashes disruptive innovation, and a proven team that has had a consistent out-sized success in entrepreneurial and high-growth settings.”


Baya Systems will make its public debut at DAC 2024 in San Francisco (June 23-27).

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