Why The Continuing Industry Paranoia?

13th September 2010
ES Admin
June’s market numbers were horribly boring says Malcolm Penn, Chairman & CEO of Future Horizons on publication of The Global Semiconductor Monthly Report. “12:12 semiconductor industry growth continued to slow, exactly as we said it would,” he adds, “from last month’s 45.4 to ‘only’ 38.5%, quarterly month on month numbers showed the same ‘boom, boom, bust’ unit growth dynamics and ASPs continued to recover.
There were absolutely no surprises and consequently no changes to the Future Horizons July IFS forecast. And with the first half year growth now up 50.4% versus the first half of 2009, 11.1% versus the second half of this year, Penn says even a flat second half yields a year on year growth rate of 28%, bringing the chip market up to US $290billion.

“But … (surprise, surprise … not!),” Penn continues, “the growth rates are now slowing; they were unsustainable and are a reflection of the equally unsustainable negative rates this time last year. But, in today’s superficial balance sheet engineering driven world, any hint of a slowing is enough to trigger global paranoia at the expense of common sense, logic and clear thinking; the dark side of Dan Bricklin and Bob Frankston’s 1979 VisiCalc, the world’s very first spreadsheet invention.”
The big question Malcom Penn keeps asking – and he emphatically states he just doesn’t get an answer to is just what exactly is wrong with a world GDP growth outlook of ‘only’ 4.3% for 2011-11?

And under 3nm...
Picking up on the semiconductor scene, Future Horizons also spotlights the sub-3nm design challenge. As transistors continue to shrink, new hurdles constantly appear, the most significant being that effects previously insignificant start to become a major factor. Recent examples of this are when the delay of interconnects began to exceed that of the devices and when the leakage of the devices significantly exceeded design expectations. This latter problem, says the report, was the direct result of transistor models not accurately taking account of increased gate leakage when transistors that were supposed to be off were not totally so.

The gate leakage problem arose because the gate region was only 5~10 atoms thick, and it is this rapid reduction in the number of atoms in a transistor that harbingers the sub-3nm IC design problem. With an ever-smaller number of atoms involved in the transistor operation, the atomic level effects start to become highly significant. These include the boundaries between the gate, drain and source terminals whereby the channel will no longer be smooth with respect to their size but have to be considered as rough edges. In addition, the thickness of the gate insulator can no longer be considered uniform and, as we currently cannot place dopant atoms in exact positions within a crystal lattice, the effect of where a single dopant atom is situated also starts to become significant.

To deal with these and other issues, TCAD software is becoming more prominent, modelling IC designs in 3D. One of the most important parameters to be analysed as the proximity of devices and interconnects shrinks is the electro-magnetic field effects. However the problem of atomic level effects is now also becoming significant so the industry is beginning to use a concept called variability whereby we define probabilities of how a transistor will operate at any given time and then use this variance in each individual transistor in multiple simulations of the circuit to determine if it will ever fail in a real situation.

You can obtain the full report at

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