The device shows dramatically superior gate reliability (NBTI) over Si channel devices due to a unique energy band structure of the compressively-strained Ge channel.
According to Aaron Thean, logic devices program director at imec: “We are facing significant challenges to scale the MOSFET architecture towards 7nm and 5nm. Besides dimension scaling, enhancing the device performance, in the face of rising parasitics and power, is a major focus of the logic device research at imec. Among the key activities are R&D efforts investigating both high-mobility channel material and new methods of enhancing Si-based FinFET.”
With options to introduce heterostructure into next-generation FinFET, quantum-well channels based on a combination of materials that enhance both mobility and electrostatics, can be engineered. At VLSI 2013, imec also presented comprehensive simulation work that investigated material combinations of Si, SiGe, Ge and III-V channels to enhance device electrostatics, providing important process guidance to extend FinFET scalability.
Moreover, imec presented novel highly scalable engineering approaches to tune gate workfunction and improve mobility, noise and reliability in Si nMOS finFETs. The impact on the performance of layout-induced stress effects in scaled finFETs and the impact of random telegraph noise (RTN) fluctuation in lowly doped devices was shown.
Imec’s research into next-generation finFETs is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.