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Multitest’s UltraFlat Process Meets Requirements of High Parallel Vertical Probe Card Applications
Lattice Semiconductor and Aptina announce dual image sensor stereo camera reference design for CES 2012

Multitest’s UltraFlat Process Meets Requirements of High Parallel Vertical Probe Card Applications

Multitest announces that its UltraFlat process meets the requirements of high parallel vertical probe card applications. For applications such as DDR3 memory, the requirements for the flatness of boards at wafer-level testing become crucial. For optimizing MLO/MLC attachments and contact element interfaces, a better surface is needed. Additionally, flatter PCBs require less compliance from the probe interface and reduce interface wear.
5 January 2012
byNews Desk

Leveraging the knowledge of PCB stack up engineering and PCB construction, Multitest developed the new “UltraFlat™” process to meet these requirements. UltraFlat™ allows for a very tight overall flatness tolerance to be maintained by removing the bow/twist in the PCB. Unlike “flat-baking” that provides a temporarily flat PCB, Mutltitest’s UltraFlat™ process provides a permanent overall flatness for the PCB.

With UltraFlat™, Multitest typically is able to comply with bow/twist requirements of 1.0 percent.

5 January 2012
byNews Desk

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