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Real Intent’s CTO Speaks about Improving Electronic Design Verification Efficiency with Automatic Formal Analysis
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Real Intent’s CTO Speaks about Improving Electronic Design Verification Efficiency with Automatic Formal Analysis

Dr. Pranav Ashar, Real Intent’s CTO, will speak about Improving Verification Efficiency with Rule Based Automatic Formal Analysis at the 7th annual International System-on-Chip Conference in Newport Beach, California.

Real Intent, Inc. is known as the innovator in automating the intelligence of formal technologies for electronic design verification.

Dr. Pranav Ashar rejoined Real Intent this year and previously served as the company’s CTO from 2004 to 2006. He previously worked at NEC Labs (Princeton, NJ) developing formal verification technologies for VLSI design. He authored about 70 papers and co-authored a book titled Sequential Logic Synthesis. He holds a Ph.D. in EECS from UC Berkeley.

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