LatticeECP3 Device Is First Low Cost FPGA To Support Broadcom HiGig Protocol

The HiGig MAC ensures that the Media Access rules specified in the 802.3ae IEEE standard and HiGig Protocol definitions are met while transmitting a frame of data over Ethernet. On the receive side, it extracts the different components of a frame and transfers them to higher applications through a FIFO interface. With this new Lattice IP core, designers will be able to implement low cost network solutions using Broadcom devices.

Compliant with Broadcom HiGig and HiGig2™ protocol definitions, the HiGig MAC IP core has a 64-bit wide internal data path operating at a maximum frequency of 156 MHz on the LatticeECP3 FPGA. The core provides XGMII and XAUI interfaces to the PHY layer and supports variable-sized packet transmission with fixed-sized messaging capability (HiGig2 only). With multicast address filtering and 16-bit statistics counters, the core requires approximately 4100 FPGA look-up tables (LUTs) for HiGig implementations and approximately 4700 FPGA LUTs for HiGig2 implementations.

“Broadcom continues to expand the vibrant HiGig ecosystem and we are pleased to welcome Lattice to the growing number of partners that support HiGig,” said John Mui, Senior Product Line Manager at Broadcom Corporation. “The low power LatticeECP3 FPGA family, coupled with the HiGig IPcore from Lattice, provides a cost effective platform for interfacing with Broadcom devices, enabling high speed Ethernet solutions for the Service Provider, Data Center and Enterprise markets,”

“The small footprint HiGig MAC IP core will help designers develop bridging and switching solutions with Broadcom devices,” said Lalit Merani, Lattice Senior Product Marketing Manager. “This is another example of how Lattice has responded to the needs of its customers by focusing on low-cost and low-power design with the LatticeECP3 FPGA family.”

The HiGig MAC IP core developed by Lattice is supported by Lattice’s IPexpress™ FPGA design tool module. Included as a standard feature in the Lattice Diamond™ design environment, the IPexpress module significantly reduces design time by allowing IP parameterization and timing analysis on the designer’s desktop. This allows users to customize Lattice's extensive library of IP functions for their unique applications, integrate them with their proprietary FPGA logic designs and evaluate the overall device operation via simulation and timing analysis prior to making any IP purchase commitments.