Cavium and Lattice have already begun executing their plan to demonstrate SRIO interoperability, and both companies will announce updates as they become available. “The addition of the SRIO interface in the OCTEON II processors, along with the wide variety of other standards-based interfaces, provides a new low-latency connectivity option,” said Tasha Castañeda, Senior Strategic Alliance Manager, Cavium Networks. “We are pleased to add Lattice to Cavium’s PACE (Partnership to Accelerate Customer End-solutions) ecosystem in order to offer our customers a strong FPGA design solution.”
“Lattice is excited to be working with Cavium Networks. This SRIO interoperability testing will strengthen our rich portfolio of wireless IP. We are working to introduce future bridging applications for the OCTEON II and our ECP3 family, including SRIO to CPRI, SRIO to PCIe and SRIO to SGMII,” said Ted Marena, Director of Business Development for Lattice.