Innovative Silicon’s David Fisch to Present on Z-RAM Memory Scalability at IWFIT 2007

28th August 2007
ES Admin
Innovative Silicon Inc.(ISi), the developer of Z-RAM high-density memory intellectual property, has announced that David Fisch, director of product architecture, will present a paper on Zero Capacitor RAM (Z-RAM) and its scalability path to 32-nm and beyond. The talk will take place at 11 a.m. on Wednesday, September 5, at the 7th International Workshop of Future Information Technology (IWFIPT) in Dresden, Germany.
During the presentation, Fisch will discuss Z-RAM memory and its comparison to other embedded memories. Z-RAM technology harnesses the floating body effect of silicon on insulator (SOI) semiconductor devices and provides manufacturing advantages over standard bulk silicon memory technologies. It is ideal for Systems-on-Chip (SoC), microprocessors and portable consumer applications requiring low power, high density and high speed. Moreover, the technology has just been licensed by Hynix for use in future stand-alone DRAM chips. The discussion will also include an examination of Z-RAM memory cell features, as well as design and architectural considerations.

“With each new technology node, the challenges of building a robust, scaleable embedded memory grow and in turn drive higher process complexity and cost along with increased investments in capital equipment,” said Jeff Lewis, vice president of marketing, Innovative Silicon. “Despite these factors, the resulting memory macros reflect increasingly difficult trade-offs between power, speed and density.

To effectively deal with these trends, today’s designers require a good understanding of the existing range of memory technologies, including Z-RAM, in order to make the optimal memory choice for any given application.”

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