Evatronix Enhances its USB Portfolio with High Speed Inter-Chip (HSIC) Compatible PHY IP
Evatronix SA, the leading provider of USB-IF certified solutions for SuperSpeed USB 3.0 and USB 2.0 IP, have announced today the introduction of a High Speed Inter-Chip (HSIC) compatible PHY IP for significant power and area savings in USB 2.0 chip-to-chip connections.Impl
“The introduction of the USBHSIC-PHY is the next step in the Evatronix strategy of delivering complete USB solutions,” said Wojciech Sakowski, Evatronix CEO. “With a silicon-proven suite of controllers, software stacks and OS drivers already in our portfolio, we are now complementing our offering with the USBHSIC-PHY to enable straightforward implementation of the USB 2.0 chip-to-chip connectivity with all components from a single IP vendor.”
Through the implementation of a 240MHz DDR interface the HSIC standard provides full support for the 480Mbps data transfer of the USB protocol. By elimination of 3.3 and 5V signaling the HSIC interface enables significant silicon area and power savings in comparison to standard cable USB 2.0 PHYs.
22nd February 2024
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