Better area, speed & power trade-offs with CoolCube technology
CEA-Leti today announced its first results towards the demonstration of CoolCube’s feasibility in FinFET technology on its 300mm production line and new CoolCube circuit designs that improve the trade off between area, speed and power. Key process steps developed on 300mm wafers show progress in closing the gap between the demonstration of a single device and taking the technology to fabrication.
CoolCube is Leti’s sequential integration technology that enables the stacking of active layers of transistors in the third dimension. Under development for eight years, it aims at fully benefiting from the third dimension, and is enabled by cutting in half the thermal budget in manufacturing transistors, while maintaining their performance.
Mobile devices, where minimal power consumption is key, are the primary market for chips manufactured with the technology. CoolCube also allows designers to include backside imagers in the chips and co-integration of NEMS in a CMOS fabrication process also is possible.
“CoolCube enables local via density that is 10,000 times higher than ‘standard’ 3D integration, because the technology is designed to connect stacked active layers at a nanometric scale,” said Maud Vinet, CMOS Laboratory Manager, Leti. “In the digital area, we expect this 3D technique to allow a gain of 50% in area and 30% in speed compared to the same technology generation in classic 2D – gains comparable to those expected in the next generation. In heterogeneous integration, we expect CoolCube to be an actual enabler of smart-sensor arrays by allowing a close integration of sensors, detection electronics and digital signal processing.”
Product Spotlight
APV1111GVY
Panasonic
Panasonic PhotoMOS® Photovoltaic MOSFET High-Power Drivers
| SKU: | |
|---|---|
| Stock: | 3490 |
| Cost: | $3.95 |
