Altera's RapidIO IP Core Passes RIOLAB Device Interoperability Testing

RIOLAB is the world's only independent RapidIO interoperability testing facility. DIL-3 is RIOLAB's final stage of device interoperability testing and ensures Altera's internally developed Serial RapidIO IP is interoperable with components, systems and software using RapidIO technology. The IP core works with Altera's Arria®, Cyclone® and Stratix® FPGAs and HardCopy® ASICs.

Altera's Serial RapidIO MegaCore function is designed to the RapidIO interconnect specification version 1.3. The core supports x1 and x4 lane widths at 1.25-Gbps, 2.5-Gbps and 3.125-Gbps lane rates, and allows for physical-, transport- and logical-layer separation. The endpoint IP core comes complete with test benches that provide proven interoperability with leading digital signal processor and switch vendors.

Altera offers a complete system-level, integration-ready Serial RapidIO solution that includes a Serial RapidIO IP core, reference designs and hardware development platforms. Designers can create custom systems to support their RapidIO architectures, including processor endpoints, digital signal processor endpoints with signal processing megafunctions, RapidIO switches, and a variety of RapidIO bridges that include PCI, PCI-X, HyperTransport™, system memory, and peripheral devices.

“Serial RapidIO is the interconnect technology of choice for many wireless, military and medical system designers who require a high level of security, data management and quality of service,” said Luanne Schirrmeister, senior director of component product marketing at Altera. “For these designers, passing RIOLAB's DIL testing gives them the added confidence that Altera's devices and RapidIO IP core are compatible and interoperable within their RapidIO system.”