Altera’s high-performance Stratix IV GX FPGAs feature integrated transceivers with data rates up to 8.5 Gbps along with up to four PCIe hard IP blocks supporting end-point and root-port applications. The device’s PCIe IP blocks embed all layers of the PCIe protocol stack, including the physical layer, data-link layer and transaction layer. The IP blocks are PCIe 1.1 and PCIe 2.0 compliant in x1-, x4- and x8-lane configurations.
Our 40-nm Stratix IV family delivers the highest performance, best-in-class transceivers and a rich set of optimized IP to accelerate time-to-market in high-performance applications, said Luanne Schirrmeister, senior director of component product marketing at Altera. Passing PCI-SIG compliance testing enables users to choose Stratix IV GX FPGAs for their PCIe designs without worry. It is yet another successfully executed milestone met by our industry-leading engineering team.
Stratix IV GX FPGAs support leading-edge high-bandwidth applications by delivering unprecedented system bandwidth with superior signal integrity. Featuring up to 48 low-power transceivers operating between 600 Mbps and 8.5 Gbps, Stratix IV GX FPGAs offer a complete, programmable solution for the growing number of applications and protocols requiring high-speed serial transceivers. In addition to support for PCIe, Stratix IV GX FPGAs support a wide range of protocols including Serial RapidIO®, Gigabit Ethernet, XAUI, CPRI (including 6G CPRI), CEI 6G, GPON, SFI-5.1 and Interlaken.