Wireless

Microchip unveils terabit-scale secure ethernet PHY family with port aggregation

20th September 2022
Sheryl Miles

The demand for increased bandwidth and security in network infrastructure driven by growth in hybrid work and geographical distribution of networks is re-defining borderless networking.

Led by AI/ML applications, the total port bandwidth for 400Gbp/s (gigabits per second) and 800Gbp/s is forecasted to grow at an annual rate of over 50%, according to 650 Group.

This growth is expanding the transition to 112Gbp/s PAM4 connectivity beyond just cloud data centre and telecom service provider switches and routers to enterprise ethernet switching platforms.

Microchip Technology is responding to this market inflection with the META-DX2 Ethernet PHY (physical layer) portfolio by introducing a family of META-DX2+ PHYs. These are the first to integrate 1.6Tbp/s (terabits per second) of line-rate end-to-end encryption and port aggregation to maintain the most compact footprint in the transition to 112Gb PAM4 connectivity for enterprise ethernet switches, security appliances, cloud interconnect routers and optical transport systems.

“Introduction of four new META-DX2+ Ethernet PHYs demonstrates our commitment to supporting the industry transition to 112Gb PAM4 connectivity powered by our META-DX retimer and PHY portfolio. In conjunction with our META-DX2L retimer, we now offer a complete chipset for all connectivity needs from retiming, gearboxing, to advanced PHY functionality,” said Babak Samimi, Corporate Vice President of Microchip’s communications business unit. “By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, datacentre, and service provider switching and routing systems that can offer pay-as-you-need enablement of advanced features including end-to-end security, multi-rate port aggregation, and precision timestamping via software subscription model.”

META-DX2+’s configurable 1.6Tbp/s datapath architecture outperforms the next near competitors by 2x in total gearbox capacity and hitless 2:1 protection switch mux modes enabled by its ShiftIO capability. The flexible XpandIO port aggregation capabilities optimise router/switch port utilisation when supporting low-rate traffic.

Also, the devices include IEEE 1588 Class C/D Precision Time Protocol (PTP) support for accurate nanosecond timestamping required for 5G and enterprise business critical services. By offering a portfolio of footprint-compatible retimer and advanced PHYs with encryption options, Microchip enables developers to expand their designs to add MACsec and IPsec based on a common board design and Software Development Kit (SDK).

META-DX2+ differentiated capabilities include:

  • Dual 800 GbE, quad 400 GbE and 16x 100/50/25/10/1 GbE MAC/PHY
  • Integrated 1.6T MACsec/IPsec engines that offload encryption from packet processors so systems can more easily scale up to higher bandwidths with end-to-end security
  • Greater than 20% board savings compared to competing solutions that require two devices to deliver the same 1.6Tbp/s gearbox and hitless 2:1 mux modes
  • XpandIO enables port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimised for enterprise platforms
  • ShiftIO feature combined with a highly configurable integrated crosspoint enables flexible connectivity between external switches, processors, and optics
  • Device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes including programmability to optimize power vs. performance
  • Support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications

“As the industry transitions to a 112Gbp/s PAM4 serial ecosystem for high-density routers and switches, line-rate encryption and efficient use of port capacity becomes increasingly important,” said Alan Weckel, Founder and Technology Analyst at 650 Group, LLC. “Microchip’s META-DX2+ family will play an important role in enabling MACsec and IPsec encryption, optimising port capacity with port aggregation, and flexibly connecting routing/switching silicon to multi-rate 400G and 800G optics.”

Like the META-DX2L retimer, the series of META-DX2+ PHYs can be used with Microchip’s PolarFire FPGAs, the ZL30632 PLL, oscillators, voltage regulators, and other components that have been pre-validated as a system to help speed designs into production.

Development tools

Microchip’s 2nd-gen Ethernet PHY SDK for the META-DX2 family lowers development costs with field-proven API libraries and firmware. The SDK supports all META-DX2L and META-DX2+ PHY devices within the product family. Support for the Open Compute Project (OCP) Switch Abstraction Interface (SAI) PHY extensions are included to enable agnostic support of the META-DX2 PHYs within a wide range of Network Operating Systems (NOS) that support SAI.

Availability

The META-DX2+ family is expected to sample during the fourth calendar quarter of 2022.

See the META-DX2L Ethernet PHY at ECOC 2022

Microchip will be exhibiting the META-DX2L PHY device, which started sampling in the fourth quarter of 2021, at the European Conference on Optical Communication (ECOC) 18 – 22 September 2022 in Basel Switzerland.

Microchip and other OIF members will be showcasing how multi-vendor interoperability is accelerating industry solutions for the global network at the Congress Centre Basel.

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