Tessent White paper – reversible scan chain diagnosis
The semiconductor industry is seeing very complicated silicon defect types and defect distribution for advanced technologies, resulting in scan chain diagnosis becoming more difficult.
To improve the resolution of scan chain diagnosis, Tessent Diagnosis can use new scan chain test patterns to leverage a reversible scan chain architecture.
Key paper insights
- Scan chain diagnosis is used to identify yield limiters in all phases of yield ramp.
- Test chips are used as characterization vehicles during the technology qualification stage.
- Scan chain failures could account for up to 66% of chip failures.
- Tessent can leverage reversible scan chain architectures to improve scan chain diagnosis resolution.
- The advantage of this method is that only chain test patterns are required for diagnosis and the process runs much faster.
- Enabling reversible chain diagnosis requires small changes to the design and the design flow.
This White paper describes how reversible scan chain diagnosis works, how to generate patterns, presents design flows, and shows silicon results of reversible chain diagnosis.