Sondrel accelerate implementation of ASIC designs
Sondrel has revealed its family of Architecting the future IP platforms are easy to modify to precisely match customers’ ASIC requirements.
This is because of its scalable architecture framework (SAF) that they are all based on. This uses re-usable, modular IP blocks that each have a wrapper containing a standardised set of functions and interfaces. Each Architecting the future IP platform has been created by assembling the required blocks to meet the performance and functionality required for a particular application area.
“It is like building blocks that have standardised studs that interconnect them,” explained Rowan Naylor, Sondrel’s Principal System Architect.
"With a core chassis that blocks connect onto. Now blocks of different sizes and types can be repositioned in the chassis to make way for new ones without having to completely start the whole design again from scratch that you would normally have to.
"This is because we have created a standard for the configurable interfaces of the wrappers that encapsulate each IP block with supporting functions and services, such as clock reset and power management, so that it is less work to connect them as well as reposition them for customisation. The standards will also mean that we can quickly create a wrapper for any IP supplied by the customer or from a third party.”
Graham Curren, Sondrel’s CEO, added: “There is nothing new about re-using IP but the practical implementation is invariably quite complicated as there is no universal standard for IP block interfaces so design time has to be spent on customising IP block interfaces for each implementation. Sondrel works over a wide range of application areas giving us a unique perspective so we could see how IP blocks could be re-used from one area to another if they had standardised interfaces.
"So, we created our Scalable Architecture Framework that uses modularisation with standard interfaces to give us a fast-track way to practically re-use IP blocks and add and change as required. In one instance, for example, we were able to shave six months off the design time of an ASIC with this new approach.”
Sondrel used SAF to create the first five members of the Architecting the future family of IP platforms that are each designed to have virtually everything needed for an ASIC solution for a particular application area. The standardised modular approach means that, at the start of a new customer project, Sondrel selects the appropriate IP platform and then customises it by adding more computing blocks for improved performance or different functionality with the appropriate block from its library of blocks to create a bespoke solution.
Third party or customer IP, once wrapped, is similarly added into the design. The overall result is that SAF enables Sondrel to dramatically reduce design time by having an effective way to rapidly assemble solutions for customers and save them design costs as well as enabling them to have a product in the market significantly faster.
“We believe that we are the first company to have created such a framework that enables IP to be effectively and easily reused in a standardised modular way,” added Graham Curren. “Many have tried in the past to do this but we think are the first to have successfully done so as a solution that can be easily used across so many application areas.”
Graham Curren, concluded: “This ‘blocks’ approach is particularly useful when the specification for the ASIC changes partway through the design process as often happens when the customer refines requirements as the project progresses. Normally, such changes could require a complete redesign to include new features or additional computing power but now, with SAF, the modules are added onto or removed from the chassis. This saves our customers huge amounts of time and money and underpins our driving force of Architecting the future of ASIC design.”
SAF is based on a ‘chassis’ that encapsulates the foundation services and resources required in the class of application, i.e., transport fabric (NoC/NiC), system memory, power-clock-reset domains and system management (Boot, configuration, FuSa and general application management functions). All the IP blocks connect and communicate with each other via the chassis to ensure easy integration and rearrangement, unlike design methodologies where blocks connect directly to other blocks requiring complete redesign if changes are needed.
Extensive use of Sondrel’s modelling processes allows the dimensioning and configuring of the chassis with regards to both the bus fabrics and the memory subsystem(s). The modelling also covers how the data processing requirements are partitioned across multiple heterogeneous processing slices for each mode of operation to meet power and performance constraints. The SAF then enables the integration to be performed in a reliable and predictable way.
The blocks equate to the compute and IO functions (CPUs, DSPs, PCIe etc.) that are implemented in subsystems based on ‘slices’. Each slice has standard services and interfaces for interworking, synchronisation and communication. This approach enables the performance to be scaled by increasing the number used so, for example, three identical slices nominally triple the computing power. Additional functionality can similarly be easily integrated by plugging the appropriate modular slice onto the chassis. Using slices also cuts overall project time as every slice in the library has been previously tested and verified, which also reduces project risk.