Immunity to single-event upsets is achieved using a redundant architecture, where two identical and parallel powertrains with fault-tolerant control ICs are housed in a single high-density SM-ChiP package.
Advanced communication satellites require high power density and low noise. Vicor soft-switching, high-frequency ZCS/ZVS power stages within metal-shielded ChiPs, reduce the power system noise floor, enabling signal integrity and total system performance with the requisite high level of reliability.
The complete power-source-to-point-of-load solution consists of four SM-ChiPs: the BCM3423, a 100V nominal, 300 watt K = 1/3 bus converter in a 34x23mm package; the PRM2919, a 33V nominal 200W regulator in a 29 x 19mm package; and two VTM2919 current multipliers, a K = 1/32 with an output of 0.8V at 150A and a K = 1/8 with an output of 3.4V at 50 amps. The solution powers the ASIC directly from the 100V power source with minimal external components and low-noise operation.
All of the modules are available in the Vicor high-density SM-ChiP package with BGA (ball grid array) connections and optional solder mask for the top and bottom surfaces. Operating temperature for the ChiPs is -30 to +125°C.