Time-based ECG readout chip designed for wearables
imec and Holst Centre, an open-innovation initiative set-up by imec and TNO, have presented a 0.6V ECG readout chip in 40nm technology based on time-domain circuit techniques. The chip maintains consistent beat detection capabilities, even under movement (~40mVpp), paving the way to a low cost, low power multi-sensor SoC solution for wearable medical applications.
There is a clear need for emerging applications in personal healthcare to add more digital signal processing capabilities and memory storage within the system itself. While today’s digital ICs and memory ICs benefit from technology scaling in terms of power and area, this has yet to be achieved for analogue readout electronics. Current state-of the-art analogue circuit techniques don’t result in a significantly reduced area in scaled technologies and, due to the accompanied reduced supply voltage with scaled technologies, the AFE readout chip faces significant challenges in combining a large dynamic range with small size and low power consumption.
The ECG readout chip is only 0.015mm2 implemented in TSMC 40nm CMOS. It can handle up to 40mVpp AC sigma and up to 300mV DC-electrode offset while consuming only 3.3µW from a 0.6V supply. By acquiring an ECG signal from the noise-stress database, the system does not saturate and is able to maintain a consistent beat detection capability even in presence of vigorous motion (~40mVpp). This was achieved by implementing a time-domain-based readout architecture, which leverages the benefits of technology scaling and it avoids the need for area intensive analogue circuitry, such as high-gain amplifiers and passives. The readout chip achieves performance that is comparable with current state-of-the-art implementations at a fraction of the area.
Nick Van Helleputte, Team Leader, Biomedical Circuits, imec, commented: “Our breakthrough readout ECG chip paves the way to low-cost, low-power multi-sensor systems for ambulatory medical applications. Furthermore, it opens additional innovation paths for beyond 40nm AFE design, leveraging the power and area benefits of scaled technology in digital architectures.”