Custom flows achieve certification for TSMC N3 process
Cadence Design Systems has announced that its digital full flow and custom tool suite has been optimised for TSMC’s 3nm (N3) process technology. The Cadence tools have achieved the latest Design Rule Manual (DRM) and SPICE certification for TSMC’s N3 process.
These innovations assist in driving and delivering next-generation mobile, AI and HPC applications, developed on the N3 process technology, with innovative reference flows and methodologies. Cadence and TSMC continue to work closely with customers on production designs on TSMC’s advanced-process technologies.
The certified tool suites support the Cadence Intelligent System Design strategy, enabling customers to achieve SoC design excellence. Cadence’s integrated digital and custom flow is fully convergent and all tools work together seamlessly. Customers can download the corresponding N3 process design kit (PDK) to begin design projects now.
The Cadence integrated digital full flow has been updated and certified for use on TSMC’s N3 process technology. The flow features enhanced physical optimisation and timing signoff closure. It includes the Innovus Implementation System, Liberate Characterisation, Liberate Variety Statistical Characterisation, Quantus Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution and Pegasus Verification System. Additionally, the Genus Synthesis Solution and its predictive iSpatial technology is enabled for these process technologies for mobile, AI and hyperscale designs.
The Cadence digital suite and available reference flows help customers achieve better power, performance and area (PPA) while designing on TSMC’s N3 process. Some of the tool suite enhancements that enable customers to successfully design mobile, AI and HPC systems with improved PPA include, improved extraction accuracy, updated routing rules, accurate LVF-generation during characterisation and robust support of advanced colouring.
The Cadence custom tool suite has been certified on TSMC’s N3 process. The certification includes the Virtuoso Custom IC design platform, consisting of the Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso ADE Product Suite, the Voltus-Fi Custom Power Integrity Solution, and the Spectre Circuit Simulation Platform, which includes the Spectre X Simulator.
Cadence has continuously improved its custom design methodologies and capabilities within the Virtuoso Advanced-Node Platform for use with TSMC’s advanced-process technologies. Customers continue to achieve better custom design throughput versus traditional design methodologies using the advanced capabilities within the Virtuoso platform. Custom enhancements for TSMC’s N3 process technology include expanded 3nm design rule support, custom digital colour remastering, enhanced analogue cell support, additional productivity improvements with an enhanced device-level P&R flow and a front-to-back legacy-node design migration flow.
“By continuing to extend our collaboration with Cadence, we’re providing support for our customers that are designing the next generation of mobile, AI and HPC systems using our latest N3 process,” said Suk Lee, Senior Director of the Design Infrastructure Management Division at TSMC. “Our latest work enables our customers to design with the tools, benefitting from the significant power and performance boost of TSMC’s 3nm process technology and to quickly launch their new product innovations to market.”
“We’ve continued to work closely with TSMC to enable our customers to take advantage of the most advanced technologies required to support today's emerging mobile, AI and HPC applications,” said Dr Chin-Chi Teng, Senior Vice President and General Manager of the Digital & Signoff Group at Cadence. “Based on latest N3 certification from TSMC and our joint successes with customers on N7 and N5 designs, customers are now evaluating our digital reference flow on TSMC’s N3 process technology to take their designs to the next level.”