Aerospace & Defence

Microchip unveils MPU family for a new era of autonomous space computing

9th July 2024
Paige West

Microchip Technology has launched the first devices in its PIC64 High-Performance Spaceflight Computing (PIC64-HPSC) microprocessors (MPUs) family.

This launch comes as the space hardware and service industry is projected to grow significantly, with the World Economic Forum estimating a CAGR of 7% from $330 billion in 2023 to $755 billion by 2035.

Advancing space computing

The PIC64-HPSC MPUs mark a departure from traditional spaceflight computing solutions, offering radiation and fault-tolerant capabilities with widely adopted RISC-V CPUs. These CPUs are augmented with vector-processing instruction extensions to support AI/ML applications, enhancing autonomous capabilities for space missions. The MPUs include a range of industry-standard interfaces and protocols previously unavailable in space applications, supported by a growing ecosystem of partners providing integrated system-level solutions. This ecosystem includes Single-Board Computers (SBCs), space-grade companion components, and a network of open-source and commercial software partners.

Enhanced capabilities for diverse applications

The PIC64-HPSC RH (Radiation-Hardened) MPUs provide local processing power for autonomous missions, such as hazard avoidance on the Moon’s surface, while also enabling long-duration deep-space missions with extremely low-power consumption. The PIC64-HPSC RT (Radiation-Tolerant) MPUs are designed for Low Earth Orbit (LEO) constellations, balancing cost-effectiveness with high fault tolerance for reliable and secure space operations.

Key features of the PIC64-HPSC MPUs include:

64-bit MPU Architecture: eight SiFive RISC-V X280 64-bit CPU cores supporting virtualization and real-time operation, with vector extensions delivering up to 2 TOPS (int8) or 1 TFLOPS (bfloat16) of performance for AI/ML processing.

High-speed network connectivity: a 240Gbps Time Sensitive Networking (TSN) Ethernet switch for 10GbE connectivity, scalable PCIe Gen 3 and Compute Express Link (CXL) 2.0, and RMAP-compatible SpaceWire ports with internal routers.

Low-latency data transfers: RDMA over Converged Ethernet (RoCEv2) hardware accelerators for low-latency data transfers from remote sensors, maximising compute capabilities by bringing data closer to the CPU.

Defence-grade security: defence-in-depth security with support for post-quantum cryptography and anti-tamper features.

High fault-tolerance: dual-Core Lockstep (DCLS) operation, WorldGuard hardware architecture for partitioning and isolation, and an on-board system controller for fault monitoring and mitigation.

Flexible power tuning: dynamic controls to balance computational demands with tailored activation of functions and interfaces.

Strategic partnerships and future directions

In 2022, NASA selected Microchip to develop a High-Performance Spaceflight Computing processor capable of delivering at least 100 times the computational capacity of current spaceflight computers. This partnership has led to the development of the PIC64-HPSC MPUs, promising significant advancements for future space missions.

Microchip’s PIC64-HPSC MPUs will be featured at the IEEE Space Compute Conference 2024 in Mountain View, California, where representatives from NASA, Microchip, and industry leaders like Northrop Grumman will discuss the technology and its ecosystem. Key sessions include:

  • Conference Keynote: Dr. Prasun Desai, Deputy Associate Administrator, Space Technology Mission Directorate, NASA, will discuss the agency’s strategy for advanced computing and HPSC technology investment
  • HPSC Workshop: Insights from Prasun Desai, Microchip, JPL speakers, and Northrop Grumman’s Kevin Kinsella on the HPSC program and its significance for spaceflight computing

Comprehensive ecosystem and tools

The PIC64-HPSC MPUs are supported by a comprehensive ecosystem featuring flight-capable SBCs, a community of software partners, and commercial standards to streamline system-level integrated solutions. Early ecosystem members include SiFive, Moog, IDEAS-TEK, Ibeos, 3D PLUS, Micropac, Wind River, Linux Foundation, RTEMS, Xen, Lauterbach, and Entrust.

Microchip also offers an evaluation platform incorporating the MPU, an expansion card, and various peripheral daughter cards.

Pricing and availability

PIC64-HPSC samples will be available to Microchip’s early access partners in 2025. For more information, contact a Microchip sales representative or visit Microchip's PIC64-HPSC MPU ecosystem partners webpage.

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