Design

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Software suite accelerates design workflows

Software suite accelerates design workflows
PathWave Design 2020 includes the latest releases of Keysight’s electronic design automation software to accelerate design workflows for radio frequency (RF) and microwave, 5G, and automotive design engineers.  The suite includes releases of PathWave Advanced Design System (ADS) 2020, PathWave RFIC Design (GoldenGate) 2020, PathWave System Design (SystemVue) and PathWave RF Synthesis (Genesys).
5th June 2019

SoC monitoring supports intelligent heterogeneous IP designs

SoC monitoring supports intelligent heterogeneous IP designs
It has been announced by UltraSoC that Wave Computing has chosen the company’s embedded analytics and heterogeneous debug technology to test its new TritonAI 64 scalable IP platform for intelligent SoCs (systems on chip). Wave Computing’s use of UltraSoC’s platform will also serve as a reference design for customers needing to validate and debug heterogeneous IP designs.
5th June 2019

Java-on-a-Chip for fast controller development

Java-on-a-Chip for fast controller development
The availability of Java on a Chip (JoC), a small Java-programmable module designed and made by demmel (Austria) for industrial use, has been announced by Saelig Company. Java on a Chip (JoC) is a Java-programmable module, designed for innovative smart applications. The highly integrated Java-programmable JoC Module can replace conventional microcontroller electronics, minimise programming and development time, and simplify hardware design.
5th June 2019


Cloud program can accelerate chip design projects

Cloud program can accelerate chip design projects
The launch of Cadence Design Systems Cloud Passport Partner Program aims to give customers a proven and easier path to the cloud when their internal IT teams desire assistance. Cadence has engaged with program members to ensure they are knowledgeable and proficient at deploying Cadence tools in cloud-based electronic design environments.
3rd June 2019

Circuit simulator delivers 10X performance gains

The Spectre X Simulator from Cadence Design Systems is a massively parallel circuit simulator designed to provide up to 10X performance gains, while maintaining accuracy in analogue, mixed-signal and RF applications. The simulator can solve 5X larger designs when compared to previous simulation solutions, enabling customers to effectively simulate circuits containing millions of transistors and billions of parasitics in a post-layout verification flow.
3rd June 2019

Considering the trade offs of different fan bearing designs

Considering the trade offs of different fan bearing designs
Fans are a vital element of many electronic systems, designed to keep the device operating within recommended temperatures, while making sure the electronics are working at their optimum level. Attempts have been made to find alternative thermal management methods, with none proving as effective and economical as the fan. By Ryan Smoot, CUI Inc.
3rd June 2019

Duo enable Astera Labs to develop PCIe 5.0 Retimer SoC

Duo enable Astera Labs to develop PCIe 5.0 Retimer SoC
Synopsys has announced that Astera Labs successfully utilised Synopsys' Fusion Design Platform, Verification Continuum Platform, and Design Services to develop its breakthrough connectivity technology for next-gen servers, all running on AWS. The collaboration represents two industry milestones: the first large-scale design fully implemented and verified from start to finish on a third-party public cloud, and the first PCIe 5.0 retimer for heterogenous compute and workload-optimised servers.
31st May 2019

eSPI bus technology supports new computing with next-gen chipsets

eSPI bus technology supports new computing with next-gen chipsets
  Microchip has announced the first commercially available eSPI-to-LPC bridge. The ECE1200 bridge allows developers to implement the eSPI standard in boards with legacy LPC connectors and peripherals. This allows the developers to implement the eSPI standard while preserving large investments in legacy LPC equipment and substantially minimising development costs and risk.
30th May 2019

Prototyping system scales to multi-MHz performance for billion gate designs

Prototyping system scales to multi-MHz performance for billion gate designs
Verification Suite and System Innovation offerings have been expanded at Cadence Design Systems with the announcement of the Protium X1 Enterprise Prototyping Platform, a data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019

Enterprise prototyping system for early software development

Enterprise prototyping system for early software development
It has been announced that Cadence Design Systems has expanded its Verification Suite and System Innovation offerings with the Cadence Protium X1 Enterprise Prototyping Platform, the first data centre-optimised FPGA-based prototyping system providing multi-MHz speed for early software development, hardware/software regressions and full system validation.
29th May 2019


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Sensor+Test 2019
25th June 2019
Germany Nürnberg Messe
The Digital Healthcare Show 2019
26th June 2019
United Kingdom EXCEL, London
unbound london 2019
17th July 2019
United Kingdom Old Truman Brewery, London
DSEI 2019
10th September 2019
United Kingdom EXCEL, London
EMO Hannover 2019
16th September 2019
Germany Hannover