Oasys Design Systems

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Oasys Design Systems Articles

Displaying 1 - 10 of 10
8th April 2013
Oasys Design Systems Announces Register Retiming Capability

Oasys Design Systems announced today that register retiming capability for improved quality of results is now available in the Oasys RealTime synthesis engine. The Oasys RealTime synthesis engine is the core technology of the Oasys RealTime Explorer and Designer products, the only EDA tools that produce the same implementation accurate results for RTL exploration and physically-aware synthesis.

13th February 2013
Oasys Design Systems Joins the TSMC Soft-IP Alliance Program

Oasys Design Systems revealed today that it has joined the TSMC Soft-IP Alliance Program to enable TSMC IP partners with a new RTL exploration tool to improve quality of results and reduce the iterations required for design closure.

3rd June 2011
Oasys Design Systems adds DFT Capabilities to Chip Synthesis

Oasys Design Systems today announced that its Chip Synthesis platform, in use in production environments, now includes design for test (DFT) capabilities, further extending the fast speed and high capacity of Oasys’ RealTime Designer software.

24th February 2011
Oasys Design Systems Enhances Chip Synthesis with Power Capabilities

Oasys Design Systems today unveiled the latest version of its revolutionary Chip Synthesis platform with enhanced capabilities that include chip-level power analysis and the ability to re-synthesize a design from the register transfer level (RTL) with new power constraints.

14th February 2011
Gary Meyers Named to Oasys Design Systems’ Board of Directors

Gary Meyers, an experienced electronic design automation (EDA) and semiconductor executive, has been named to the Board of Directors of Oasys Design Systems, provider of Chip Synthesis™, a fundamental shift in how synthesis is applied to integrated circuit (IC) design and implementation.

9th November 2010
Oasys Design Systems Names Craig Robbins Vice President of Sales

Oasys Design Systems announced today that Craig Robbins, a noted electronic design automation executive, has assumed the role of senior vice president of sales, reporting to Paul van Besouw, Oasys’ president and chief executive officer.

20th September 2010
Oasys Design Systems Adds SystemVerilog Support To RealTime Designer

Oasys Design Systems announced today that it has added support for SystemVerilog to RealTime Designer™, its revolutionary new Chip Synthesis platform used in production flows at leading-edge semiconductor and systems companies worldwide.

20th September 2010
Verific, Oasys Design Systems Extend Tool Partnership

Verific Design Automation, supplier of de facto standard front-end software to the EDA and semiconductor community, announced today that Oasys Design Systems has expanded its relationship by licensing Verific’s SystemVerilog front-end software for RealTime Designer™. Previously, Verific licensed its VHDL analyzer to Oasys. As a result, design teams using RealTime Designer, Chip Synthesis™ software capable of synthesizing register transfer...

18th June 2010
Oasys Design Systems’ Announces Multi-Year Strategic Chip Synthesis Technology License with Xilinx

Oasys Design Systems today announced its multi-year strategic licensing agreement with Xilinx for Oasys’ revolutionary Chip Synthesis™ technology. The companies are not disclosing terms of the agreement or details regarding Xilinx’s long-term plans for implementing the technology for field programmable gate array (FPGA)-based design.

18th June 2010
Juniper Networks Selects RealTime Designer from Oasys for Next-Generation Networking Chip Designs

Oasys Design Systems today announced that Juniper Networks® has selected RealTime Designer™, a revolutionary new Chip Synthesis™ platform, for the design of its next-generation networking chips. “After a thorough evaluation, we determined that RealTime Designer offers high-quality results and performs very well in our environment,” said Debashis Basu, vice president for Silicon Development at Juniper Networks. “It is a great tool tha...

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