You can now build power efficient AI and m/l applications requiring small form factors the neural network IP enables network descriptions built on tensorflow and onyx to be changed on the fly without re-synthesising the FPGA code. Simultaneous CN NS can also be run on a single core vector blocks IP instantiation. To find out more about smart embedded vision from microchip, visit their website and watch the video below.
Software and neural network IP for smart embedded vision
You don’t need to be an FPGA expert to port your trained convolutional neural network into polar phi FPGAs, that’s because Microchip’s call vector blocks neural network IP and vector blocks accelerator software development kit includes Python and C++ based tool flows for each based inferencing with the Pola fire FPGAs that consume up to 50% lower power over mid-range alternatives.
