The 25V MOSFET also features a gate-drain charge/gate-source charge ratio that reduces switching related power loss.
It reaches the lowest RDS(ON) in its class by reducing any switching-related power loss.
This is achieved by optimising the total gate charge (Qg), gate-drain charge (Qgd) and Qgd/gate-source charge (Qgs) ratio. The very low Qgd Miller Effect charge enables passing through plateau voltage faster.
The device is a 100% Rg and UIS tested TrenchFET Gen IV MOSFET.
Typical applications include synchronous rectification, high power density DC/DC, synchronous buck converter, OR-ing, load switching and battery management.
The MOSFET is housed in the conventional PowerPAK SO-8 design, delivering higher power density with no change to its package dimension or its pin configuration.
A 10mil clip reduces any package-contributed resistance by 66%, maximising the performance of the silicon.
