These advancements provide design and DFT engineers with an alternative for silicon validation while reducing debugging time and cost, enabling them to verify their new silicon with no capital investment, set up their own test environment within a few hours and be ready to test when the device arrives from the fab.
Visitors can see live demonstrations of how fast the desktop test station can verify a device with STIL-generated DFT patterns.
With free tester leasing and minimum maintenance costs, Advantest’s CTS allows customers to avoid unplanned expenses.