IC Validator extends support for emerging process nodes and FinFET technology with new four-colour patterning decomposition and verification support. Certified signoff runsets at 28nm and below for all major foundries are available today.
IC Validator is the key technology enabler for In-Design physical verification in the IC Compiler and IC Compiler II place and route solutions. IC Validator In-Design in the 2015.06 release introduces timing- and density-aware track-based metal fill that offers higher density than foundry fill while maintaining pre-fill design timing. Additionally, In-Design automated DRC repair refinements now deliver a fix rate of greater than 80%, with many designs achieving fix rates of 100%.
Advances in process technology and ever-increasing design complexity have placed growing demand on physical verification products to check many more design rules. This evolution has created intense interest among IC designers in a new physical verification solution geared specifically to address these challenges. IC Validator is a comprehensive physical verification product including DRCs, layout-vs.-schematic checks, programmable extended electrical rule checking and metal fill insertion. IC Validator’s modern architecture and excellent multi-core scalability make it the signoff tool of choice for a growing number of designers, from those developing small analogue chips to those designing the largest, most advanced digital chips.
Bijan Kiani, Vice President of Marketing, Synopsys’ Design Group, commented: “We are committed to providing the best physical verification signoff solutions for our customers working with the leading foundries and at the latest emerging technology nodes. A growing number of leading customers are adopting IC Validator and realising the advantages of In-Design when tackling their growing physical verification challenges.”
