At the core of this transformation are 2.5D and 3D advanced semiconductor packaging technologies. These approaches are based on the concept of chiplet design, where functional blocks, such as compute, memory, and I/O, are disaggregated and fabricated on the most suitable process nodes, then integrated into a single package. In 2.5D packaging technologies, chiplets are placed side by side on an interposer, while 3D architectures stack them vertically. This modular integration improves system performance, reduces cost, and offers greater design flexibility. These benefits are essential for meeting the demanding requirements of AI and HPC workloads.
However, rising AI workloads are pushing higher thermal design powers (TDPs) and driving tighter integration through advanced packaging, intensifying thermal management challenges due to limited area for heat dissipation.
In this article, IDTechEx explores the power and thermal challenges associated with 3D-stacked chips, as well as the emerging solution trends the industry is adopting or proposing for both 2.5D and 3D packaging technologies. The insights are based on IDTechEx’s latest report, ‘Thermal Management for Advanced Semiconductor Packaging 2026-2036: Technologies, Markets, and Opportunities’, which offers a comprehensive analysis of thermal management strategies for advanced semiconductor packaging technologies.
Power challenges in 3D-stacked chips
In 3D-stacked chips, power delivery becomes significantly more complex than in 2D because of increased current density, limited pin access, and the use of vertical interconnects. A k-tier 3D stack draws approximately k times the current of a 2D chip with the same footprint, but power pins and packaging resources do not scale accordingly. This imbalance leads to multiple challenges. TSVs used in power delivery introduce substantial resistance, typically around 1Ω per stack, resulting in greater IR drop and difficulty maintaining a stable supply voltage. Power is typically delivered through the bottom tier, which must carry the cumulative current for the entire stack, making it especially vulnerable to voltage droop and dynamic noise.
This is further complicated by the fact that power-hungry compute blocks are often located near the heat sink, also on the bottom tier. Meanwhile, effective decoupling is hindered by limited white space, as TSVs and dense routing reduce the area available for placing decoupling capacitors. These combined effects worsen voltage fluctuation across the stack, increasing performance variability, timing uncertainty, and reliability risks, especially under peak-load conditions.
Thermal challenges in 3D-stacked chips
Thermal management is one of the most critical bottlenecks in 3D-stacked chips. Unlike 2D designs, where heat dissipates laterally and upward toward the heat sink, 3D stacks consist of thinner dies that limit lateral heat spreading. In addition, the middle dies are prone to heat accumulation, as they are farther from the heat sink and have limited effective thermal escape paths. Moreover, the vertical heat removal path is limited by the low thermal conductivity of inter-die materials such as dielectric layers and bonding adhesives. This leads to thermal hotspots that degrade performance and reduce reliability due to increased leakage and stress on interconnects.
Another key issue is the close proximity of high-power logic blocks and memory can result in significant thermal coupling between tiers, further complicating thermal design. Conventional cooling methods often fail to reach the buried layers effectively, making it necessary to consider alternative techniques such as thermal TSVs and chip-level microfluidic cooling. However, these methods introduce their own trade-offs in terms of design complexity, cost, and integration challenges.
Materials innovations for more efficient heat transfer
To support more efficient thermal management in both 2.5D and 3D semiconductor packaging, the industry is actively exploring several innovative solutions. One key area of focus is the development of advanced thermal interface materials (TIMs). The IDTechEx report, ‘Thermal Management for Advanced Semiconductor Packaging 2026-2036: Technologies, Markets, and Opportunities’, offers a detailed analysis of TIM technologies, particularly emerging materials for TIM1 and TIM1.5. These materials include options such as liquid metal, indium foil, graphene sheets, and next-generation thermal gels with silver fillers for enhanced thermal conductivity.
In parallel, there is a shift away from the traditional two-layer TIM structure (TIM1 and TIM2) toward a single TIM1.5 layer. This approach aims to reduce thermal resistance by minimising material interfaces. While this may reduce the number of TIM layers used, it does not necessarily shrink the overall market, as TIM1.5 materials tend to command higher unit costs due to their demanding technical specifications. IDTechEx forecasts that the combined market for TIM1 and TIM1.5 for advanced semiconductor packaging will grow to approximately $500 million by 2036, highlighting a substantial commercial opportunity.
Beyond TIMs, another promising area of research is the use of diamond, particularly copper-plated diamond, as a substrate material for high-end semiconductor packaging. The IDTechEx report also delves into the latest developments, technical challenges, and future prospects surrounding the integration of diamond substrates into advanced packaging architectures.
Liquid cooling, immersion cooling, and microfluidic cooling
Beyond material innovations, active liquid cooling is becoming an increasingly important trend in advanced thermal management. In high-performance data centres, technologies such as direct-to-chip and immersion cooling have already reached commercial deployment. Notably, the adoption of cold plate cooling in NVIDIA’s GB200 and NVLink72 configurations in the previous year has further solidified its position as the dominant near-term solution. IDTechEx expects cold plate cooling to remain the leading approach for at least the next two-three years.
However, both cold plate and immersion cooling primarily address heat dissipation from the chip package to the ambient environment. The more pressing thermal challenge lies within the packaging itself, specifically, managing the heat generated between vertically stacked components in 3D packaging architectures. To date, the industry has yet to establish a clear solution for this issue.
IDTechEx identifies microfluidic cooling as a promising candidate for addressing this internal thermal bottleneck, despite the complexity involved in its implementation. Microfluidic cooling uses intricate networks of microchannels to circulate liquid coolant either within the package lid or directly inside the packaging structure. While various architectural configurations are under development, the technology still faces several hurdles, including high design and manufacturing complexity, concerns about scalability, and limited data on long-term reliability.
The IDTechEx report, provides a comprehensive analysis of the transition from 2.5D to 3D advanced semiconductor packaging, advancements in power delivery methods (e.g., backside power and through-silicon vias), thermal challenges associated with 3D-stacked chips, the use of innovative thermal materials (such as thermal interface materials and diamond substrates), and the implementation of liquid cooling techniques, including direct-to-chip, immersion, and microfluidic cooling systems.
The IDTechEx report provides an in-depth analysis of ongoing R&D efforts in microfluidic cooling and outlines potential architectural roadmaps for its future adoption in advanced semiconductor packaging.
Key contents from the report include:
- A 10-year area forecast for TIM1 and TIM1.5 for advanced semiconductor packaging, segmented by material type including liquid metal, graphene sheet, indium foil, and thermal gel
- A 10-year market size forecast for TIM1 and TIM1.5 for advanced semiconductor packaging, segmented by these materials
- A 10-year volume forecast for microfluidic cooled advanced semiconductor packaging units
- A 10-year market size forecast for liquid cooling for high-end data centre semiconductors, segmented by direct-to-chip/cold plate and immersion
