Synopsys announced its ongoing close collaboration with TSMC to deliver multi-die solutions, encompassing advanced EDA and IP products that support TSMC’s processes and packaging technologies, driving innovation in AI and multi-die design. The 3DIC compiler exploration-to-sign off platform and IP, tuned for 3D packaging, alongside the company’s parternship with TSMC on design enablement has resulted in multiple customer tape-outs.
Building on Synopsys‘ continued collaboration with TSMC is the availability of certified digital and analog flows, along with the enabled Synopsys.ai on TSMC’s N2P and A16 processes using TSMC NanoFlex architecture. Additionally, Synopsys provides robust automotive IP solutions for TSMC N5A and N3A processes and best-in-class Interface and Foundation IP solutions, delivering highest level of safety, security and reliability while enabling maximum performance with the lowest power for advanced chips.
“Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape outs on the industry’s most advanced packaging and process technologies,” said Michael Buehler-Garcia, Senior Vice President, Synopsys. “With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC’s advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market.”
“TSMC has been working closely with our long-standing Open Innovation Platform (OIP) ecosystem partners like Synopsys to help customers achieve high quality-of-results and faster time-to-market for leading-edge SoC designs,” said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division, TSMC. “With the ever-growing need for energy efficient and high-performance AI chips, the OIP ecosystem collaboration is crucial for providing our mutual customers with certified EDA tools, flows and high-quality IP to meet or exceed their design targets.”
Synopsys’ analog and digital flows, along with the enabled Synopsys.ai, are certified on TSMC N2P and A16 processes using TSMC NanoFlex architecture to help optimise performance, power, and to scale chip designs to advanced semiconductor technologies. Certified capabilities for designs on TSMC A16 Super Power Rail (SPR) process improve power distribution and system performance, while maintaining thermal robustness of backside routing designs. Synopsys’ pattern-based pin access methodology has been enhanced for TSMC A16- node to deliver competitive area results.
In addition, Synopsys is collaborating with TSMC on the design flow development for TSMC’s A14 process and its first process design kit release scheduled for the later part of 2025.
Synopsys IC Validator signoff physical verification solution is certified for TSMC A16 process to support DRC and LVS checking. IC Validator’s high-capacity elastic architecture seamlessly scales PERC rules to handle TSMC’s N2P full-path electrostatic discharge (ESD) verification with improved turnaround time.
Synopsys‘ 3DIC Compiler’s unified exploration-to-signoff platform has been enabled to support the TSMC-SoIC (SoIC-X) technology, including 3D stacked designs and silicon interposer and bridge with CoWoS technologies, resulting in several customer tape outs. With 3DIC Compiler, customers can achieve higher productivity and faster turnaround times with the platform’s automated UCIe and HBM routing, TSV and bump planning, and multi-die signoff verification.
The ongoing collaboration between Synopsys and TSMC on silicon photonics has also enabled an AI-optimised photonic IC flow for TSMC-COUPE technology to deliver enhanced system performance and address multi-wavelength and thermal requirements in multi-die and AI designs.
