Quartus II software v9.1 builds upon the productivity advantage Altera consistently delivers with its design software. The software provides the industry’s fastest compile times for high-end FPGAs, averaging a 20 percent reduction annually over the past five years. The compile time advantages in the latest release are driven by more efficient place and route algorithms, improved multiprocessor support and faster timing-driven synthesis.
Rapid Recompile for Faster Design Iteration
The new Rapid Recompile feature enhances the Quartus II software’s ability to further minimize design compilation times. Rapid Recompile maximizes designer productivity when making small engineering change order (ECO)-style design changes after a full compile is run, reducing compilation times by 50 percent on average versus running another full compile on the design. Rapid Recompile also significantly improves designer productivity during timing closure by preserving critical timing during late design changes.
Expanded Device Support for New Cyclone IV FPGAs
The three smallest Cyclone IV GX devices will be supported in the Quartus II design software v9.1 with the remaining Cyclone IV devices supported in the Quartus II design software v9.1 service pack 1. To see the press release for the Cyclone IV family, announced today, visit www.altera.com/corporate/news_room/releases/2009/products/nr-cyclone-iv.html. This version of the Quartus II software also offers support for the Stratix® IV E EP4SE820 FPGA, the industry’s highest density FPGA at 820K logic elements (LEs). Offering software support for Altera’s latest FPGA families enables customers to get a jump start on the latest Cyclone and Stratix FPGA designs today.
