Design
System certified for 65nm to 14nm FinFET processes
Cadence Design Systems has announced that GLOBALFOUNDRIES certified the Cadence PVS for custom/analog, digital and mixed-signal design physical signoff for 65nm to 14nm FinFET process technologies. The certification covers Cadence-qualified PVS rule decks for physical verification used in Cadence Virtuoso® Integrated Physical Verification System, Cadence Encounter Digital Implementation System and full-chip signoff.
Kit aids in the development of motor control applications
The MultiMotor Series Development Kit, from Zilog, aids in the development of motor control applications using an assortment of Zilog MCUs designed specifically for motor control environments. The Z16FMC MCU-based MultiMotor Series Development Kit (ZMULTIMC100ZCOG) is a complete application-specific platform for creating a design featuring a Zilog motor control MCU Module connected to a 3-phase MultiMotor Series Development Board. ...
STMicroelectronics adopts IC comiler for CPU & GPU implementation
Synopsys has announced that STMicroelectronics has standardized on Synopsys' IC Compiler place-and-route solution for all its CPU and GPU implementations inside its Design Enablement and Services organization. STMicroelectronics processor cores are known for pushing gigahertz performance with extreme energy efficiency, making them a compelling choice for the mobile market place.
Interactive tool enables engineers to modify power designs
WEBENCH Schematic Editor, an editing and simulation feature that enables engineers to customize power management designs and simulate the circuit created within the WEBENCH environment, has been launched by Texas Instruments.
Compiler enables 3x productivity & 5x performance improvement
A product which represents a compelling vision of SoC verification technology and verification roadmaps has been unveiled by Synopsys. Verification Compiler is a complete portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure.
TI announce the first IoT-capable LaunchPad
The first IoT-capable LaunchPad in the TI ecosystem, the Tiva C Series Connected LaunchPad has been introduced at a price of just $19.99 (USD). This IoT platform enables engineers to rapidly prototype a variety of cloud-enabled applications, bringing expansive connectivity to any new or existing LaunchPad-based applications.
ASIC design methodology meets DO-254 avionics requirements
The digital ASIC design flow methodology employed by ON Semiconductor supports the stringent requirements of commercial aircraft manufacturers that need to obtain DO-254 certification. A DO-254 compliant solution is an essential aspect of any system-on-a-chip designed for use in flight critical avionics applications.
Environment speeds PCB timing closure by up to 67%
Speeding timing closure by up to 67%, Cadence Design Systems has announced that the Allegro TimingVision environment is now available within Cadence Allegro PCB Designer. This environment makes it possible for PCB designers to save significant time in ensuring that signals in an interface meet timing requirements.
Web tool enables quick search & comparison of inductors
A web tool has been launched which allows users to quickly find and compare inductors based on their exact operating conditions: current, ripple, frequency and ambient temperature. The Power Inductor Finder web tool, from Coilcraft, instantly calculates core and winding losses, computes temperature rise, and plots L vs. I curves for up to six parts on the same graph.
SoC selected to expand Datang's 4G deployment in China
The dual-mode TD-SCDMA/TD-LTE SoC, from Broadcom, has been selected by Datang Mobile to develop a new family of enterprise and residential small cell solutions. Broadcom's small cell SoCs provide the architecture for Datang Mobile to meet growing demand for high-performance data services in China and expand deployment of its 4G TD-LTE network while minimizing operation costs.