The AD9557 dual-input multiservice line card adaptive clock translator and the AD9558 quad-input multiservice line card adaptive clock translator translate any standard input frequency to any standard output frequency from 2 kHz to 1.25 GHz with sub-400-fs RMS total jitter on 12 kHz to 20 MHz. The new clock translators outperform traditional PLL (phase-locked loop) designs that require the addition of expensive VCXOs (voltage-controlled crystal oscillators).
The built-in programmability of the AD9557 and AD9558 clock translators allow network line card designers to use the same component in many different board designs, limiting the number of components needed and reducing overall system cost. This includes synchronisation for a wide variety of high-performance applications, including data communications, next-generation wired networking applications, telecommunications, test and measurement, high speed data acquisition and wireless base station controllers.
The AD9557 and AD9558 clock translators integrate an on-chip, low-phase-noise, frequency-agile VCO and loop filter along with dynamic adaptive clock support. Adaptive clocking allows the DPLL (digital PLL) divider ratios to be changed while the DPLL is locked. This enables the frequency value at the output to be dynamically adjusted by up to +/- 100ppm from the nominal output frequency without manually breaking the loop and reprogramming the part with a sub 0.1 ppb step in frequency resolution. This adaptive clock function is used for applications such as SDH to OTN mapping/demapping and asynchronous mapping/demapping. The adaptive clock translators’ programmable DPLL supports loop bandwidth from 0.1 Hz to 5 kHz and features three separate programming modes for ease of use and flexibility. The two devices are pin- or soft-pin pre-configured to support popular SONET/SDH, Ethernet, Synchronous Ethernet and Fiber Channel frequencies, while SPI (serial port interface) and I2C ports are available to program customised input-to-output frequency translation.
At 6 mm x 6 mm and 9 mm x 9 mm in size, respectively, the AD9557 and AD9558 clock translators provide compact, frequency agile, cost effective clocks for line card designers. The AD9557 features two reference inputs (single-ended or differential) and two pairs of clock outputs. Each output pair is configurable as a single differential LVDS/HSTL output or as two single-ended CMOS outputs. The AD9558 offers the same features but with four reference inputs and six pairs of clock outputs.
Key Features of the AD9557 and AD9558 Adaptive Clock Translators
• Supports GR-1244 Stratum 3 stability in holdover mode.
• Provides smooth reference switchover with virtually no disturbance on output phase.
• Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 Systems.
• Supports ITU-T G.8262 Synchronous Ethernet slave clocks.
• Supports ITU-T G.823, G.824, G.825, and G.8261.
The AD9557 and AD9558 clock translators are well suited to work with the asynchronous AD9577 clock generator with dual PLLs to provide key elements of the clock tree for various applications. The AD9577 is a cost-effective asynchronous clock solution for oscillator replacements and generates local clocks for processors, FPGAs, or PHYs in SONET/SDH, Synchronous Ethernet applications, Ethernet enterprise switches, core/edge router fabric cards and line cards as well as in packet transmission networks (PTN) and fiber channel applications.