MMB processor enables 10% die size reduction

23rd October 2014

Synopsys Inc

Siobhan O'Gorman

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To achieve a 10% reduction in total die size while maintaining product quality and performance, Marvell Semiconductor have utilised Synopsys' MMB (Multi-Memory Bus) processor for it's networking SoC. The processor, from Synopsys' DesignWare STAR Memory System, allowed Marvell to accelerate silicon bring-up and achieve silicon success.

A test solution that would minimise area and routing congestion without affecting performance or quality was required for Marvell’s design, which includes hundreds of memory instances. The logic needed to implement a test and repair strategy for all memory instances mapped on a multi-memory test bus is contained within the MMB processor. Saving over 50% in memory test logic area, Synopsys’ solution allowed Marvell to use a single processor to test hundreds of memories.

The MMB processor allows designers to either decouple test logic from the block under test or, to minimise the impact on performance and area, optimally place the test logic within the block. The processor enables high-performance design blocks and processor subsystems with L1 and L2 caches.

Allowing designers to implement high test coverage, reduce design time, lower manufacturing test costs and maximise manufacturing yield, the DesignWare STAR Memory System is an automated pre- and post-silicon memory test, diagnostic and repair solution. To identify prevalent memory defect mechanisms at every process node and develop the test algorithms so to detect them, Synopsys utilises rigorous simulation and silicon characterisation methods.

"Using the DesignWare STAR Memory System has significantly reduced our silicon area and cost," said Sohail Syed, Senior Director of Engineering, Marvell. "We were able to not only reduce total die size by 10%, but also meet our stringent product quality goals and high performance requirements by using the MMB processor. In addition, the STAR Memory System's Yield Accelerator and Silicon Browser tools have significantly improved our silicon bring-up efforts by making test pattern development and validation more efficient."

John Koeter, Vice President of Marketing for IP and Prototyping, Synopsys, commented: "Synopsys provides robust test solutions that enable designers to meet their challenging performance, power and area requirements without compromising on quality. With the addition of the MMB processor in the DesignWare STAR Memory System, designers can reduce their on-die test footprint and maintain high performance while implementing comprehensive memory test solutions for faster time to volume."