Design
MCU maths libraries help maintain ultra-low power consumption
Leveraging intelligent peripherals and optimised software to ease the burden of complex maths instructions, Texas Instruments has announced an expanded ecosystem of free and easy-to-use maths libraries for its MSP430 MCUs. Both MSPMATHLIB and IQmathLib software libraries are suitable for applications where performance and power are critical, such as orientation tracking.
DAQ software upgraded to include CAN traffic analyzer
The configuration and data acquisition software IPEmotion 2014 R1 has been upgraded to include a number of new features, including graphical filling level indication at A2L file import, new table display instrument and audio playback in analysis. The IPETRONIK business division IPEmotion, who released the upgraded software, highlights the CAN traffic analyzer as a key new feature.
PROFINET IRT connectivity added to RapID platform
Providing cycle times down to 250µs, Innovasic announces an updated version of its RapID Platform Network Interface for PROFINET IRT and RT connectivity. Cycle times down to 31.25µs are supported on the same hardware platform as soon as the high performance profile is released by PROFIBUS PROFINET International.
Initiative aims to accelerate mixed-signal SoC design verification
An initiative to accelerate the verification of mixed-signal SoC designs has been announced by Synopsys. The company has launched the initial components of the initiative, which include a SystemVerilog-based methodology, AMS Testbench, and the VCS AMS mixed-signal verification solution that incorporates VCS functional verification and the CustomSim FastSPICE simulator.
Model-based PLE reduces development costs by 62%
Atego has claimed that the recently launched Atego Vantage is the world’s first integrated solution combining Model-based Systems and Software Engineering (MBSE), Asset-based Modular Design (SoS/CBD/SOA) and variable Product Line Engineering (PLE). This combination into Model-based Product Line Engineering (MB-PLE) can reduce development costs by 62% and bring 23% more projects in on time.
Tool chain helps develop auto systems using coaxial cables
Consisting of several elements that together provide everything needed to develop a MOST150-based automotive system or device using coaxial cables, the MOST150 coax (cPHY) tool chain has been unveiled by K2L. The toolchain provides application development, whole-system safeguarding, testing, simulation, deep-system analysis, verification, and stress scenarios.
Design tool delivers 10x physical design throughput
Synopsys have presented what they call a 'game-changing' successor to their IC Compiler, offering ultra-high-capacity design planning, unique clock-building technology and advanced global-analytical closure techniques. The IC Compiler II has been built from the ground up on a completely new, multi-threaded infrastructure.
HD SoC enables on demand cable TV throughout China
Enabling the deployment of cable services to millions of China cable subscribers, Inspur Group has selected Broadcom's BCM7583 HD SoC to power the company's set-top boxes (STBs). The SoC combines cost-effective design and high-performance capabilities, allowing operators to enhance services while reducing overall cost.
Cadence tools reduce leakage power by 50% in smartphone chip
Yamaha has used components of the Cadence Low-Power Solution to achieve a 50% reduction in leakage power in its latest chip for smartphones. Yamaha selected Cadence Encounter RTL Compiler, Cadence Encounter Conformal Low Power and Cadence Encounter Digital Implementation System.
IC Compiler deployed for hierarchical design implementation
MediaTek has initiated deployment of Synopsys' IC Compiler place and route solution for hierarchical design implementation. This collaboration extends the deployment of IC Compiler to the full flow starting from hierarchical design planning, through top and block-level place and route to final chip assembly.