Supporting the S1000D documentation standard, the latest Capital suite software release has been announced by Mentor Graphics. By using the Capital Publisher tool, users can automatically generate S1000D-compliant information packages directly from their electrical design data. This significantly reduces the costs and lead times associated with technical documentation creation.

The new Mentor Embedded Hypervisor product for in-vehicle infotainment systems, telematics, ADAS and instrumentation has been announced today by Mentor Graphics. The Mentor Embedded Hypervisor is a small footprint Type 1 hypervisor developed specifically for embedded applications and intelligent connected devices.

Mentor Graphics Corp today announced that Renesas Electronics is using the Tessent Hybrid TestKompress/LogicBIST solution to address safety critical test requirements defined by the ISO 26262 standard. The hybrid technique requires significantly less test logic to provide a complete solution including both high-compression scan test for low defects per million (DPM), and built-in self-test (BIST). Mentor’s hybrid test capability is ideal fo...

Mentor Graphics Corp today announced full interoperability between the Tessent IJTAG chip-level IP integration product and ASSET InterTech’s ScanWorks platform for embedded instruments, which includes chip, circuit board and system-level IJTAG tools. This combination of industry-leading capabilities delivers a comprehensive chip-to-system-level automated IJTAG IP integration solution, greatly simplifying the user’s ability to leverage...

Mentor Graphics has today announced the agenda for its thirteenth annual Integrated Electrical Solutions Forum. IESF 2013 is a day-long, free conference which covers all aspects of electrical and electronic design/simulation within the automotive, commercial vehicle, and off-highway industries. IESF 2013 takes place on Thursday, September 19, 2013 at the Ford Conference Center in Dearborn, Michigan, USA.

Mentor Graphics unveil that Proterra has standardized the Mentor Graphics VeSys tools for its electrical systems design and manufacture of wire harnesses. Proterra will be using the VeSys tools to help design and manufacture heavy-duty, electric drive systems, energy storage systems, vehicle control systems, transit buses, and the world's first all-electric, fast-charge transit bus.

Mentor Graphics unveil that the intelligent software-driven verification has been added to the Questa functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. As a result, engineering teams find more system level design bugs earlier in the verification process—during simulation or emulation, when they are easier and more cost effective to debug—before they...

Finding, identifying and fixing manufacturing defects and systemic yield limiters within library cells at 90nm and beyond. Stephen Pateras, product marketing director for Mentor Graphics Silicon Test product, explores Cell-Aware ATPG in this article from ES Design magazine.

Mentor Graphics announced it has expanded the Kronos Cell Characterization and Analysis platform to include embedded memories. The Kronos platform quickly produces accurate performance models for standard cells, I/Os, complex cells and embedded memories within an advanced, integrated environment. Characterization and analysis of embedded memories poses unique challenges: large circuit size can lead to excessive runtime, complex internal circuitry...

Mentor Graphics announced that SilabTech has achieved first silicon success for their latest 28nm high-speed, mixed-signal PHY IPs for PCI Express, SATA, MIPI, M-PHY and USB 3.0 in advance of the planned schedule. SilabTech succeeded using the Mentor Graphics Pyxis, Eldo, and Calibre tools for custom layout, extraction, simulation, physical verification, and DFM analysis.

Mentor Graphics unveiled that Calibre nmDRC and Calibre nmLVS rule decks for Samsung’s 14nm IC manufacturing processes have been significantly improved since first release. For example, the joint efforts have resulted in a 50% better performance over the previous release for the Calibre nmDRC design kit. The revised decks provide rapid turnaround and also reduce customers’ datacenter costs by reducing compute platform memory requirements.

Mentor Graphics announced it has collaborated with GLOBALFOUNDRIES to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform. The design kit enables mutual customers to achieve the best performance, power and area with faster design closure times.

Mentor Graphics and CaetanoBus today announced successful application of the company’s Capital software suite to the development of CaetanoBus’ flagship C5 coach. The C5 coach offers a wide range of configuration options and includes innovative electrical/electronic systems that significantly boost efficiency, safety, and reliability

Mentor Graphics Corp today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations. This joint effort has reduced Calibre nmDRC 20nm signoff runtimes by at least a factor of 3X and memory requirements by 60% compared to initial design kits released last year.

Mentor Graphics Corp today announced it has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process. The prospect of integrating a silicon photonics process with silicon-based electronics would allow adding the driver and control electronics on the same chip, greatly reducing packaging complexity and cost. Adding a pho...

Mentor Graphics and Tezzaron Semiconductor today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features.

Mentor Graphics today announced that CNH has transitioned to the latest VeSys software platform and also added a number of compatible tools from the Mentor Capital software suite, resulting in a very modern design environment.

Mentor Graphics today announced availability of the newest tool in the Capital software suite, Capital Harness TVM. This tool automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models.

Mentor Graphics today announced release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon.

Mentor Graphics Corporation today announced it has integrated the recently acquired MontaVista Automotive Technology Platform with the Mentor Embedded Infotainment Base Platform and Sourcery CodeBench and Sourcery Analyzer development tools. The new Mentor Embedded Automotive Technology Platform (ATP) is fully compliant with Yocto Project 1.3 and GENIVI 3.0, and will continue to track and support upcoming GENIVI versions.