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We enable companies to develop better electronic products faster and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip design.
The first phase of the Xpedition PCB flow to address the increasing complexity of today’s advanced systems designs has been announced by Mentor Graphics Corporation. The increasing densities of electronics products are forcing companies to develop highly compact system designs with more functionality, and at lower costs.
An Electronic Manufacturing Service (EMS) company based in Mysore, India, Kaynes Technology has selected Mentor Graphics to provide a complete design-to-manufacturing solution comprising Mentor Graphics Xpedition Enterprise, HyperLynx, Valor Process Preparation, Valor NPI and Valor Parts Library products.
The Verification Academy from Mentor Graphics has been added to, with a new SystemVerilog course and Patterns Library that together help verification engineers increase their expertise, productivity and design quality.
Mentor Graphics has announced that the Veloce emulation platform was successfully used by Barefoot Networks, a pioneer in building user-programmable and high-performance network switches, to verify its 6.5Tb/s Tofino switch. Barefoot chose the Veloce emulation platform for its high capacity, superior virtualisation technology, remote access option and proven track record in networking design verification.
The latest additions to the PADS PCB Product Creation Platform have been announced by Mentor Graphics. New Analogue/Mixed-Signal (AMS) and high-speed analysis products address engineering challenges associated with mixed-signal design, DDR implementation, and electrically-correct design signoff.
Mentor Graphics has announced the Tanner Calibre One IC verification suite as an integral part of the Tanner analogue/mixed-signal (AMS) physical design environment, creating an easy path to the proven capabilities of Calibre verification tools for Tanner EDA’s user base. This results in a dramatically-improved IC design and verification solution for Tanner customers by providing tightly-integrated access to Calibre’s physical and circuit verification, exclusively within the Tanner L-Edit layout environment.
Mentor Graphics Corporation has announced the latest release of the Catapult Platform that decreases the hardware design time from the design start to register transfer level (RTL) verification closure by 50% compared to traditional hand-coded RTL. Existing High-Level Synthesis (HLS) methodologies improve design and verification productivity up to 10X; however, the time required to close verification on the resulting RTL can potentially wipe out these gains.
Mentor Graphics Corporation has announced a collaboration with ARM to provide accessible and affordable access to Mentor’s Tanner AMS analogue/mixed-signal design flow for ARM Cortex-M0 processor-based implementations as part of the ARM DesignStart programme. The collaboration lowers the barriers to embedded and IoT device design and verification through a combination of an affordable, complete IC design tool suite and the ability to evaluate the design flow on a reference design at no cost.
Mentor Graphics Corp has announced that Samsung Foundry’s Closed-Loop DFM solution uses production Mentor Calibre and Tessent platforms to accelerate customer yield ramps. A successful yield ramp directly impacts customer product cost and time-to-market. In the Closed-Loop DFM flows, Samsung integrates its comprehensive DFM kits with its testing and manufacturing expertise to identify integrated circuit (IC) design patterns that are most likely to impact manufacturing yield, thereby helping customers improve design quality, yield, and ramp to production.
Mentor Graphics Corporation has announced that customers and ecosystem partners are expanding their use of Calibre Pattern Matching solution to overcome previously intractable IC verification and manufacturing problems. The solution is integrated into the Mentor Calibre nmPlatform solution, creating a synergy that drives these applications at IC design companies and foundries, across multiple process nodes.
Mentor Graphics has announced that Silicon Labs has selected the Analog FastSPICE (AFS) platform for circuit verification and device noise analysis of its complex pre- and post-layout analogue circuits. Silicon Labs is using AFS to analyse PLLs, data converters, wired and wireless transceivers and other specialised high performance analogue and RF circuits.
The Valor Production Plan software from Mentor Graphics Corporation has been certified by SAP as powered by the SAP NetWeaver technology platform. The integration of the Valor Production Plan tool with SAP NetWeaver streamlines PCB assembly planning, including surface mount technology (SMT), manual assembly and test, helping to improve manufacturing efficiency and reduce operational cost. The Valor Production Plan solution can add finite printed circuit board (PCB) production planning to the SAP ERP application.
Mentor Graphics Corporation has announced a comprehensive product-creation platform based on PADS PCB software that enables individual engineers and small teams to solve the engineering challenges involved in creating today’s electronic products. With increasing systems design complexity and the need for PCB, mechanical and systems engineers to access easy-to-deploy tools, the PADS platform has been extended to enable engineers to develop PCB-based systems from concept through manufacturing hand-off.
A partnership has been established by Mentor Graphics and Ixia, a provider of network testing, visibility, and security solutions. As a result, Mentor is integrating Ixia’s virtual edition test product family, IxNetwork Virtual Edition (VE), with the Mentor Veloce emulation platform to accelerate the verification of complex networking chips. As part of this collaboration, Ixia joined the Mentor OpenDoor programme.
Designed to accelerate verification and reduce the risks associated with system-on-chip (SoC) design, Mentor Graphics Corporation has announced its Mentor Emulation Services, which combines the Veloce emulation platform with expert services and IP.
Today’s consumer needs are significantly increasing PCB design and created a number of business challenges for example, increased pressure to meet delivery deadlines, the need to lower development cost, increasing product reliability and the rise of differentiated products. However, a number of internal barriers such as increasing design complexity, frequent design changes and validation of performance mean that a number of trade-offs have to be made in order to achieve these challenges.
Mentor Graphics Corporation has announced that, in collaboration with Samsung Electronics, it is delivering a wide range of design, verification and test tools and flows optimised for Samsung Foundry’s 10nm FinFET process. The announcement includes the Calibre physical verification suite, Mentor Analogue FastSPICE (AFS) platform, Olympus-SoC digital design platform and Tessent test product suite.
Mentor Graphics has announced the first entirely native UVM SystemVerilog memory VIP (Verification IP) library for all commonly used memory devices, configurations and interfaces. Mentor is adding more than 1,600 memory models to the Mentor VIP library that already supports over 60 commonly used peripheral interfaces and bus architectures.
Announcing new applications for the Veloce platform, Mentor Graphics has ushered in a new era of emulation. The new apps - Veloce Deterministic ICE, Veloce DFT and Veloce FastPath - overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows and the time it takes to review results. The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.
Mentor Graphics has signed a multi-year subscription agreement with ARM to enable early access to a broad range of ARM Intellectual Property (IP) and related technologies. This will enable Mentor to optimise its tools and methodologies for ARM-based System-on-Chip (SoC) designs.