Mentor Graphics® is a leader in electronic design automation software.
We enable companies to develop better electronic products faster and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip design.
A partnership has been established by Mentor Graphics and Ixia, a provider of network testing, visibility, and security solutions. As a result, Mentor is integrating Ixia’s virtual edition test product family, IxNetwork Virtual Edition (VE), with the Mentor Veloce emulation platform to accelerate the verification of complex networking chips. As part of this collaboration, Ixia joined the Mentor OpenDoor programme.
Designed to accelerate verification and reduce the risks associated with system-on-chip (SoC) design, Mentor Graphics Corporation has announced its Mentor Emulation Services, which combines the Veloce emulation platform with expert services and IP.
Today’s consumer needs are significantly increasing PCB design and created a number of business challenges for example, increased pressure to meet delivery deadlines, the need to lower development cost, increasing product reliability and the rise of differentiated products. However, a number of internal barriers such as increasing design complexity, frequent design changes and validation of performance mean that a number of trade-offs have to be made in order to achieve these challenges.
Mentor Graphics Corporation has announced that, in collaboration with Samsung Electronics, it is delivering a wide range of design, verification and test tools and flows optimised for Samsung Foundry’s 10nm FinFET process. The announcement includes the Calibre physical verification suite, Mentor Analogue FastSPICE (AFS) platform, Olympus-SoC digital design platform and Tessent test product suite.
Mentor Graphics has announced the first entirely native UVM SystemVerilog memory VIP (Verification IP) library for all commonly used memory devices, configurations and interfaces. Mentor is adding more than 1,600 memory models to the Mentor VIP library that already supports over 60 commonly used peripheral interfaces and bus architectures.
Announcing new applications for the Veloce platform, Mentor Graphics has ushered in a new era of emulation. The new apps - Veloce Deterministic ICE, Veloce DFT and Veloce FastPath - overcome critical system-level verification challenges in complex SoC and system designs. They run on an upgraded Veloce OS3 operating system that significantly accelerates design compile cycles, gate-level flows and the time it takes to review results. The combination of Veloce Apps on Veloce OS3 puts more capabilities into the hands of more engineers more quickly than hardware-centric strategies.
Mentor Graphics has signed a multi-year subscription agreement with ARM to enable early access to a broad range of ARM Intellectual Property (IP) and related technologies. This will enable Mentor to optimise its tools and methodologies for ARM-based System-on-Chip (SoC) designs.
Imagination Technologies has deployed the Veloce emulation platform’s virtualised testbench acceleration (TBX) technology in their internal verification flow for their PowerVR Wizard GR6500, a ray-tracing-enabled GPU. Imagination’s PowerVR Wizard architecture raises the bar for ray-traced graphics in consumer and mobile products, delivering amazing realism and performance while meeting strict power budgets and cost constraints.
Mentor Graphics has announced that the Veloce emulation platform, specifically the Codelink offering, now supports the debug of designs built with AndesCore processors, such as N10 and N13. Andes Technology Corporation is a leading Asia-based supplier of small, low-power, high performance 32-bit embedded CPU cores. Over 600m SoCs containing its CPU cores have been shipped by Andes customers.
Mentor Graphics has announced that Terminus Technology has selected the Mentor Analogue FastSPICE (AFS) Platform for verification and device noise analysis of its data converter, power management, Wireless LAN, high-speed I/O and PLL circuits.
Mentor Graphics has announced that it is collaborating with GLOBALFOUNDRIES to qualify the Mentor RTL to GDS platform. This is to include the RealTime Designer physical RTL synthesis solution and Olympus-SoC place & route system, for the current version of the GLOBALFOUNDRIES 22FDX platform reference flow.
Mentor Graphics Corporation has announced the availability of the Vista virtual platforms for the Arria 10 SoC FPGA. The Vista virtual platforms are fully functional simulation models of processor subsystems and peripherals offered as freely downloadable pre-built binaries. These accelerate embedded software development across the entire product life cycle for significant time-to-market and product development cost savings.
Mentor Graphics has announced the Veloce VirtuaLAB Ethernet environment with support for 25, 50 and 100G Ethernet. This support enables highly efficient, emulation-based verification for the massive Ethernet-based designs being created today.
Mentor Graphics has announced a new version of its ODB++ intelligent product model, a single and open data structure for transferring PCB designs into data for fabrication, assembly and test. The version 8.1 of the ODB++ product model format provides a unique virtual documentation capability which seamlessly translates all data files, drawings, and documents from PCB design through the manufacturing flow.
Mentor Graphics has announced that speciality foundry TowerJazz has adopted the Calibre Auto-Waivers product to manage foundry design rule waivers associated with embedded IP. Automated waiver management significantly reduces the time and effort spent reviewing design rule violations so that designs can get to tapeout faster, while preventing accidental escapes of legitimate design rule violations that could impact yield.
To address the advancing needs of the independent engineer, Mentor Graphics has introduced three PADS tool suites. The PCB design solutions, which include the PADS Standard, the PADS Standard Plus and the PADS Professional, combine ease of use with productive design and analysis technologies.
With its Calibre xACT parasitic extraction platform, Mentor Graphics addresses a wide spectrum of analogue and digital extraction needs, including 14nm FinFET, while minimising guesswork and setup efforts for IC designers. The Calibre xACT platform combines accuracy and TurnAround Time (TAT) by automatically optimising extraction techniques for specific process nodes, applications, design sizes and extraction objectives.
Mentor Graphics has announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre physical verification and Design For Manufacturing (DFM) platform, and the Analog FastSPICE (AFS) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.
A design flow solution, which automates the planning, assembly and optimisation of today’s complex multi-die packages, has been introduced by Mentor Graphics. The Xpedition Package Integrator is suitable for IC package and PCB co-design and optimisation. For true IC-to-package co-optimisation, the design flow incorporates a unique virtual die model concept.