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Imagination Technologies has deployed the Veloce emulation platform’s virtualised testbench acceleration (TBX) technology in their internal verification flow for their PowerVR Wizard GR6500, a ray-tracing-enabled GPU. Imagination’s PowerVR Wizard architecture raises the bar for ray-traced graphics in consumer and mobile products, delivering amazing realism and performance while meeting strict power budgets and cost constraints.
Mentor Graphics Corporation has announced the availability of the Vista virtual platforms for the Arria 10 SoC FPGA. The Vista virtual platforms are fully functional simulation models of processor subsystems and peripherals offered as freely downloadable pre-built binaries. These accelerate embedded software development across the entire product life cycle for significant time-to-market and product development cost savings.
Mentor Graphics has announced the Veloce VirtuaLAB Ethernet environment with support for 25, 50 and 100G Ethernet. This support enables highly efficient, emulation-based verification for the massive Ethernet-based designs being created today.
Mentor Graphics has announced a new version of its ODB++ intelligent product model, a single and open data structure for transferring PCB designs into data for fabrication, assembly and test. The version 8.1 of the ODB++ product model format provides a unique virtual documentation capability which seamlessly translates all data files, drawings, and documents from PCB design through the manufacturing flow.
Mentor Graphics has announced that speciality foundry TowerJazz has adopted the Calibre Auto-Waivers product to manage foundry design rule waivers associated with embedded IP. Automated waiver management significantly reduces the time and effort spent reviewing design rule violations so that designs can get to tapeout faster, while preventing accidental escapes of legitimate design rule violations that could impact yield.
To address the advancing needs of the independent engineer, Mentor Graphics has introduced three PADS tool suites. The PCB design solutions, which include the PADS Standard, the PADS Standard Plus and the PADS Professional, combine ease of use with productive design and analysis technologies.
With its Calibre xACT parasitic extraction platform, Mentor Graphics addresses a wide spectrum of analogue and digital extraction needs, including 14nm FinFET, while minimising guesswork and setup efforts for IC designers. The Calibre xACT platform combines accuracy and TurnAround Time (TAT) by automatically optimising extraction techniques for specific process nodes, applications, design sizes and extraction objectives.
Mentor Graphics has announced that TSMC and Mentor Graphics have reached the first milestone of their collaboration on 10nm EDA certification. Calibre physical verification and Design For Manufacturing (DFM) platform, and the Analog FastSPICE (AFS) Circuit Verification Platform, including AFS Mega, are certified by TSMC based on the most current version of 10nm design rules and SPICE models.
A design flow solution, which automates the planning, assembly and optimisation of today’s complex multi-die packages, has been introduced by Mentor Graphics. The Xpedition Package Integrator is suitable for IC package and PCB co-design and optimisation. For true IC-to-package co-optimisation, the design flow incorporates a unique virtual die model concept.
A Signal Integrity/Power Integrity (SI/PI) product, developed for high-speed PCB designs, has been released by Mentor Graphics. The HyperLynx addresses high-speed systems design problems throughout the design flow, starting at the earliest architectural stages through to post-layout verification.
Mentor Graphics has announced its HyperLynx Alliance, developed with key industry partners, integrating tools, data and methodology to accelerate technology adoption. The alliance leverages the HyperLynx tool suite for high-speed design and verification, deployed on cloud-based virtual labs to accelerate time to productivity.
To allow embedded developers to integrate, execute, validate and optimise software on various platforms, Mentor Graphics has introduced the Mentor Embedded Virtual Prototype Kits (VPKs) to its Vista and Sourcery CodeBench Virtual Edition products. The kit is suitable for automotive in-vehicle infotainment, ECU networks, medical and industrial applications, networking and military and aerospace product development.
The latest addition to the Mentor Graphics Xpedition platform captures the hardware description of multi-board systems, from logical system definition down to the individual PCBs, automating multi-level system design synchronisation processes to ensure team collaboration with accuracy and faster design productivity.
Berkeley Design Automation, a nanometer circuit verification company, has been acquired by Mentor Graphics. The acquisition of BDA aligns with Mentor’s goal to deliver technologies with superior performance and automation for the growing challenges of Analog/Mixed-Signal (AMS) verification.
A proposal to form a new Accellera standards committee, to investigate the standardisation of a graph-based test specification standard, has been made by Mentor Graphics. To underscore this endeavor, Mentor will make a technical donation of its existing graph-based test specification format to jump-start the standardization effort.
Mentor Graphics unveil that Proterra has standardized the Mentor Graphics VeSys tools for its electrical systems design and manufacture of wire harnesses. Proterra will be using the VeSys tools to help design and manufacture heavy-duty, electric drive systems, energy storage systems, vehicle control systems, transit buses, and the world's first all-electric, fast-charge transit bus.
Mentor Graphics unveil that the intelligent software-driven verification has been added to the Questa functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. As a result, engineering teams find more system level design bugs earlier in the verification process—during simulation or emulation, when they are easier and more cost effective to debug—before they escape into the prototype lab.
Finding, identifying and fixing manufacturing defects and systemic yield limiters within library cells at 90nm and beyond. Stephen Pateras, product marketing director for Mentor Graphics Silicon Test product, explores Cell-Aware ATPG in this article from ES Design magazine.
Mentor Graphics announced it has expanded the Kronos Cell Characterization and Analysis platform to include embedded memories. The Kronos platform quickly produces accurate performance models for standard cells, I/Os, complex cells and embedded memories within an advanced, integrated environment. Characterization and analysis of embedded memories poses unique challenges: large circuit size can lead to excessive runtime, complex internal circuitry and a variety of choices available for pin-bus models requires a high level of automation.