Mentor Graphics Corporation

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OR 97070

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Mentor Graphics Corporation articles

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Berkeley Design Automation acquired by Mentor Graphics

Berkeley Design Automation, a nanometer circuit verification company, has been acquired by Mentor Graphics. The acquisition of BDA aligns with Mentor’s goal to deliver technologies with superior performance and automation for the growing challenges of Analog/Mixed-Signal (AMS) verification. 
24th March 2014

Proposal aims to standardise a graph-based test specification

A proposal to form a new Accellera standards committee, to investigate the standardisation of a graph-based test specification standard, has been made by Mentor Graphics. To underscore this endeavor, Mentor will make a technical donation of its existing graph-based test specification format to jump-start the standardization effort.
5th March 2014

Proterra has standardized the Mentor Graphics veSys tools

Proterra has standardized the Mentor Graphics veSys tools
Mentor Graphics unveil that Proterra has standardized the Mentor Graphics VeSys tools for its electrical systems design and manufacture of wire harnesses. Proterra will be using the VeSys tools to help design and manufacture heavy-duty, electric drive systems, energy storage systems, vehicle control systems, transit buses, and the world's first all-electric, fast-charge transit bus.
16th July 2013


Questa functional verification platform with the iSDV

Mentor Graphics unveil that the intelligent software-driven verification has been added to the Questa functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. As a result, engineering teams find more system level design bugs earlier in the verification process—during simulation or emulation, when they are easier and more cost effective to debug—before they escape into the prototype lab.
15th July 2013

Mentor Graphics explore Cell-Aware ATPG

Mentor Graphics explore Cell-Aware ATPG
Finding, identifying and fixing manufacturing defects and systemic yield limiters within library cells at 90nm and beyond. Stephen Pateras, product marketing director for Mentor Graphics Silicon Test product, explores Cell-Aware ATPG in this article from ES Design magazine.
15th July 2013

Mentor Graphics Adds Embedded Memories to the Kronos Cell Characterization and Analysis Platform

Mentor Graphics announced it has expanded the Kronos Cell Characterization and Analysis platform to include embedded memories. The Kronos platform quickly produces accurate performance models for standard cells, I/Os, complex cells and embedded memories within an advanced, integrated environment. Characterization and analysis of embedded memories poses unique challenges: large circuit size can lead to excessive runtime, complex internal circuitry and a variety of choices available for pin-bus models requires a high level of automation.
24th June 2013

SilabTech’s 28nm High-Speed PHYs Delivered Ahead of Schedule with Mentor Graphics Tool Flow

Mentor Graphics announced that SilabTech has achieved first silicon success for their latest 28nm high-speed, mixed-signal PHY IPs for PCI Express, SATA, MIPI, M-PHY and USB 3.0 in advance of the planned schedule. SilabTech succeeded using the Mentor Graphics Pyxis, Eldo, and Calibre tools for custom layout, extraction, simulation, physical verification, and DFM analysis.
10th June 2013

Mentor Graphics and Samsung Optimize 14nm Process Design Kits

Mentor Graphics unveiled that Calibre nmDRC and Calibre nmLVS rule decks for Samsung’s 14nm IC manufacturing processes have been significantly improved since first release. For example, the joint efforts have resulted in a 50% better performance over the previous release for the Calibre nmDRC design kit. The revised decks provide rapid turnaround and also reduce customers’ datacenter costs by reducing compute platform memory requirements.
3rd June 2013

Mentor Graphics and GLOBALFOUNDRIES Deliver 20nm Design Kits for Advanced Design Enablement

Mentor Graphics announced it has collaborated with GLOBALFOUNDRIES to deliver 20nm design kits for the Olympus-SoC netlist-to-GDS platform. The design kit enables mutual customers to achieve the best performance, power and area with faster design closure times.
31st May 2013

CaetanoBus Streamlines its Electrical Design Processes Using Capital Software from Mentor Graphics

CaetanoBus Streamlines its Electrical Design Processes Using Capital Software from Mentor Graphics
Mentor Graphics and CaetanoBus today announced successful application of the company’s Capital software suite to the development of CaetanoBus’ flagship C5 coach. The C5 coach offers a wide range of configuration options and includes innovative electrical/electronic systems that significantly boost efficiency, safety, and reliability
30th May 2013

Mentor Graphics and TSMC Collaborate to Improve and Expand 20nm IC Physical Verification Offering

Mentor Graphics Corp today announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations. This joint effort has reduced Calibre nmDRC 20nm signoff runtimes by at least a factor of 3X and memory requirements by 60% compared to initial design kits released last year.
29th May 2013

Mentor Graphics Teams with OpSIS Foundries and Lumerical Solutions on PDK Development for IME Silicon Photonics Process

Mentor Graphics Teams with OpSIS Foundries and Lumerical Solutions on PDK Development for IME Silicon Photonics Process
Mentor Graphics Corp today announced it has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process. The prospect of integrating a silicon photonics process with silicon-based electronics would allow adding the driver and control electronics on the same chip, greatly reducing packaging complexity and cost. Adding a photonic layer and interconnects also holds the promise of solving speed bottlenecks in future computing and chip platforms.
22nd May 2013

Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5/3D-ICs

Mentor Graphics and Tezzaron Semiconductor today announced they are collaborating to integrate the Mentor Calibre 3DSTACK product into Tezzaron’s 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features.
21st May 2013

CNH Enhances Electrical Design Capabilities with Latest Mentor Graphics Capital and VeSys Software

Mentor Graphics today announced that CNH has transitioned to the latest VeSys software platform and also added a number of compatible tools from the Mentor Capital software suite, resulting in a very modern design environment.
16th May 2013

Mentor Graphics Announces Software Vital For Wire Harness Supplier Competitiveness

Mentor Graphics today announced availability of the newest tool in the Capital software suite, Capital Harness TVM. This tool automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models.
9th May 2013

Mentor Graphics Accelerates SoC and Embedded System Delivery

Mentor Graphics today announced release of the Mentor Embedded Sourcery CodeBench Virtual Edition product, a native software environment for developing embedded systems pre- and post-silicon.
29th April 2013

BridgePoint from Mentor Graphics Provides Agilent GC Instrumentation Division an Efficient Methodology for Embedded Software Development

Mentor Graphics and Agilent Technologies are pleased to announce today the use of the Mentor Graphics BridgePoint xtUML environment in the development of its Micro GC gas chromatography instruments.
18th April 2013

Mentor Graphics Delivers Simulation and Emulation Solutions to Verify Serial Attached SCSI Products

Mentor Graphics today announced hardware and software solutions to accelerate the verification of Serial Attached SCSI second-generation products, having speeds up to 6Gbps. Using the Mentor verification solutions, designers can test their SAS Gen2 devices integrated on their System-on-Chip designs, and develop and test their software drivers and applications prior to silicon being available.
8th April 2013

Mentor Graphics Empowers 32-bit Microcontroller Development with Connectivity and a Small Footprint Binary RTOS with Nucleus SmartFit

Mentor Graphics today announced the Nucleus SmartFit product, a cost-effective, binary version of the Nucleus RTOS optimized to fit the limited internal memory of 32-bit MCUs. The Nucleus SmartFit product also includes Sourcery CodeBench development tools and provides developers with broad connectivity and power consumption options for developing products based on 32-bit microcontrollers.
5th April 2013

Mentor Graphics Announces the First IP to System, UPF-based Low-power Verification Solution

Mentor Graphics today announced availability of the first, comprehensive IP to System, UPF-based low-power verification flow. The IEEE-1801 UPF has emerged as the low- power standard that enables designers to specify a design’s power intent separately from the design itself ensuring reuse, portability and greater flexibility in power management techniques.
5th April 2013


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