Design
TSMC certifies Synopsys design tools for 10nm FinFET technology
Synopsys has announced that TSMC has certified the Synopsys GalaxyDesign Platform digital and custom design tools for TSMC's 10nm FinFET process. The certification is based on the V0.9 version of the process and enables design engineering teams using TSMC's 10nm process to realise the power of IC Compiler II's high throughput. Tool certification of V1.0 process is targeted to be completed Q4 2015.
PCB design tool update speeds time-to-market
Altium Limited has announced a major update to its flagship PCB design tool, Altium Designer, at PCB West, an annual PCB design conference in Santa Clara, California. Attendees at PCB West 2015 will get an exclusive first look at all the features coming to Altium Designer 16 before its scheduled release in autumn. This update will allow engineers to realise designs quickly and free from errors, with the addition of automation and productivit...
IC Compiler II is certified on 10nm FinFET process
TSMC has certified Synopsys' IC Compiler II place and route product for V0.9 of 10nm FinFET (N10FF) process technology and are on track to work towards V1.0 completion in Q4, 2015. IC Compiler II is the successor to IC Compiler, the place and route solution for advanced designs, delivering an improvement in throughput while achieving quality-of-results that meets TSMC's certification requirements.
FPGA-based prototyping solution delivers up to 100MHz
Synopsys has announced the HAPS-80 FPGA-based prototyping systems, a part of its end-to-end prototyping solution. The HAPS-80 systems deliver up to 100MHz multi-FPGA performance and new proprietary High-Speed Time-Domain Multiplexing (HSTDM) technology.
E-book helps software engineers track bugs faster
Software engineers can spend days or weeks tracking down bugs in complex software for multicore systems-on-a-chip (SoC), often delaying new product introductions. A new eBook by ASSET InterTech explains how developers can take advantage of both trace and static analysis tools for greater insight into code execution and to identify root causes faster.
8-bit MCU dev platform facilitates CIP setup
Microchip announces an expansion of the development platform for its growing portfolio of innovative 8-bit PIC MCUs with Core-Independent Peripherals (CIPs). Designers can combine these building blocks to perform application functions autonomously, and they can be interconnected with an increasing amount of integrated intelligent analogue peripherals.
In the future, buying cars will start in virtual reality
In future, the digitisation of the car for drivers will not just start with Bluetooth interfaces for the smartphone or with autonomous driving, but as early as the visualisation, configuration and virtual purchase process. At this year’s IAA in Frankfurt, the Rocket Data Intelligence startup is presenting software for the first time which can generate virtual cars extremely rapidly and enable them to be experienced in 3D.
Cadence, Mentor Graphics & Breker collaborate
Cadence Design Systems, Mentor Graphics and Breker Verification Systems have announced that they have collaborated on a technology contribution to the Accellera Portable Stimulus Working Group. The contribution leverages the combined experience of the three companies in providing portable test and stimulus solutions, and is intended to assist the Accellera Portable Stimulus Working Group in defining a SoC verification standard that offers both ve...
CurveSelect tool updated to easily optimise protection selectivity
Eaton has integrated the amended characteristics of ‘IE3 ready’ motor protection devices into its free CurveSelect software tool. This enhanced functionality makes it even easier to compare the tripping characteristics of protection devices. Thus, the design of switchgear and distribution systems can easily be optimised to deliver maximum availability and reliability while adhering to the new European energy efficiency regulation.
Video processing IP core provides pseudo-colour mapping features
RFEL has announced updates to its flagship Video Fusion HD, video processing IP core for FPGA and SoC systems, that now has sophisticated enhancement and customisable pseudo-colour mapping features to help product designers add a competitive edge to their systems and to aid the user in overcoming the challenges of Degraded Visual Environments (DVEs).