Design
Software configures modular power systems from source to PoL
Vicor has announced the introduction of Power System Designer, its online design tool which gives system designers the means to optimise end-to-end power systems leveraging the company's Power Component Design Methodology and power components.
Valor Production Plan tool achieves SAP certification
The Valor Production Plan software from Mentor Graphics Corporation has been certified by SAP as powered by the SAP NetWeaver technology platform. The integration of the Valor Production Plan tool with SAP NetWeaver streamlines PCB assembly planning, including surface mount technology (SMT), manual assembly and test, helping to improve manufacturing efficiency and reduce operational cost. The Valor Production Plan solution can add finite printed ...
Simulation tools adopted for automotive designs
Following an extensive evaluation process, Cypress Semiconductor has selected the full Cadence RTL-to-signoff digital design flow and complete Spectre circuit simulation platform for all of its 40nm automotive chip designs. The evaluation process gave Cypress the opportunity to dramatically improve its turnaround time and productivity with the Cadence solution when compared with its previous flow.
Real-time lighting technology expands into new markets
Geomerics, an ARM company, has revealed that its Enlighten real-time lighting technology, used in huge video games such as Star Wars Battlefront, is now being deployed to create virtual show homes for the international property market. Geomerics has licensed its technology to Yugen, an Australian company who create architectural visualisations for developers selling properties off plan or for investors who are unable to visit a site.
How to get smaller, faster and smarter code
Exhibiting at IoT DevCon 2016, in California, USA, on 25th and 26th May, IAR Systems will guide visitors on how the world-leading development toolchain IAR Embedded Workbench can help developers in simplifying their development processes and getting smaller, faster and smarter code. The company will also host several conference sessions.
Cryptographic IP enables Car2x applications
EnSilica has launched the eSi-ECDSA cryptographic IP designed to help meet the high security communication and latency requirements of automotive Car2Car and Car2Infrastructure (Car2x) applications that form part of today’s emerging Intelligent Transport Systems.
Accelerate design for next-gen, high-capacity FPGAs
Altera, now part of Intel, has announced the Quartus Prime Pro design software, which further accelerates FPGA design performance and design team productivity. The software is architected to support the next-gen high capacity, highly integrated FPGAs from Intel, which will drive innovation across the cloud, data centre, IoT and the networks that connect them.
RFEL adds Wideband capability to advanced channeliser IP core
RFEL has added wideband input capability to its multi-award winning, advanced channeliser IP core, ChannelCore Flex. This meets the increasing need for ever wider bandwidth monitoring for a wide range of demanding channelisation applications such as communications, intercept, electronic warfare, security, industrial applications, COMINT, SIGINT, sonar, radio astronomy, research and software-defined radio.
Cadence enables a 60% reduction in packaging design time
Faraday Technology, a fabless ASIC/SoC and IP provider, has used Cadence OrbitIO interconnect designer and Cadence SiP Layout to reduce their packaging design time by 60% compared to their previous methodology.
Synopsys' VIP supports Micron's Hybrid Memory Cube architecture
Synopsys has announced its next-gen VIP (Verification IP) for Micron's Hybrid Memory Cube (HMC) architecture. The HMC architecture offers a high performance, low cost memory solution, with 70% less energy utilisation than existing DRAM technologies. Synopsys VC VIP for HMC enables the design of next-generation high-speed memory technologies with ease of use, fast integration and optimum performance, resulting in accelerated verification closure.