Cadence Design Systems today extended its leadership position in analog and mixed-signal chip design technologies with the introduction of dramatic improvements to its leading Virtuoso IC design platform. Cadence announced powerful performance, capacity and usability enhancements in Virtuoso IC6.1.4 that reduce overall design time while ensuring high-quality production ICs.

Cadence Design Systems today announced that IC Plus, a communication and networking IC design company in Taiwan, has adopted the Cadence Incisive verification solution with the Open Verification Methodology (OVM) and Cadence verification IP (VIP) to optimize development time while simplifying and standardizing its verification process.

Cadence Design Systems announced today that Exar Corporation has signed an expanded business agreement to establish Cadence® as its leading chip planning and mixed-signal design solutions provider. As a result of the new multi-year agreement, the Cadence Virtuoso® and Encounter® platforms, as well as the Cadence Chip Planning Solution, will make up Exar's key mixed-signal design environment for designs at 65 nanometers and below.

Cadence Design Systems today is celebrating Innovation Day, honoring the contributions Cadence employees have made to the company and the electronics industry as a whole. Having garnered more than 800 U.S. patents and an additional 150 international patents, Cadence has a long legacy of technology innovation that has enabled EDA customers to successfully create some of the world’s most recognized consumer and business products for over 20 years...

Cadence Design Systems has announced that Silicon Hive, a worldwide supplier of semiconductor intellectual property (IP), achieved the highest quality for its HiveGo mobile imaging and video decoding solutions using the Cadence Palladium III Accelerator/Emulator. Palladium technology enabled Silicon Hive to meet aggressive IP quality requirements for multi-core, multi-million-gate designs targeting mass-market consumer products.

Cadence reported third quarter 2009 revenue of $216 million, compared to revenue of $232 million reported for the same period in 2008. On a GAAP basis, Cadence recognized a net loss of $14 million, or $(0.05) per share on a diluted basis, in the third quarter of 2009, compared to a net loss of $171 million, or $(0.67) per share on a diluted basis in the same period in 2008.

Cadence Design Systems has announced that it has delivered a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation . Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform.