lorer is the first Electronic Systems Level (ESL) solution completely dedicated to power and thermal estimation. It allows modeling of complex power management scenarios and hardware architectures and addresses the needs of system architects in charge of power optimization of on-chip or on-board designs.
The integration enables designers to link the performance analysis done on Synopsys Platform Architect to the power consumption analysis of Aceplorer. The architecture captured in Platform Architect can be exported in Aceplorer to generate the relevant power model, and the performance analysis results containing power state switching and activity can be used as use case scenarios in Aceplorer to run the power consumption simulation. Once analysis is complete, Aceplorer automatically generates reports, specifications and IEEE Standard 1801-2009 or Unified Power Format (UPF) code for implementation teams.
“Our joint solution allows customers to generate power-dimensioning scenarios from software running on virtual platforms and simulate them in Aceplorer for software-driven power optimization or power aware software development,” said Ghislain Kaiser, Docea Power CEO. “Exploring both performance and power consumption axes and making trade-offs to define the optimum architecture configuration can be done by running Aceplorer and Synopsys Platform Architect together .”
“We are seeing the same market dynamics that made system-level tools necessary for analyzing the performance of new SoCs and systems architectures driving similar needs for new solutions to power modeling and estimation at the architectural level,”said Frank Schirrmeister, director of product marketing, System-Level Solutions, Synopsys. “With Docea Power joining the System-Level Catalyst program, the interoperability between our tools will open new opportunities to our common customers enabling system-level exploration of power and performance.”