Docea Power today announced new releases of Aceplorer 3.1 and AceThermalModeler 2.0. Aceplorer 3.1 features a new solver for coupled power and thermal transient simulations featuring 1000x performance gains over the previous versions and a communication protocol enabling the co-simulation of Aceplorer models with virtual platforms and performance analysis tools. AceThermalModeler 2.0 (ATM) improves its usability.

Docea Power SAS, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today officially announced the opening of its U.S. office in San Jose, CA and the incorporation of Docea Power Inc., a fully-owned subsidiary of Docea Power. The company also announced today that Ghislain Kaiser, Docea Power co-founder and CEO will head up the U. S. operations as Docea Inc. President.

At the 48th Design Automation Conference (DAC), Docea Power, the design-for-low-power company that delivers software for power consumption and thermal analysis at the architectural level, will show and introduce an enhanced version of its flagship software product, Aceplorer 2.3, with a synthetic view for capturing the power architecture of complex designs. This enables what-if analysis and optimization for hardware architecture and the target ap...

Docea Power announced today that it is shipping a new version of its Aceplorer software. Aceplorer is used to model and optimize electronic design power consumption, early in the design cycle, at the architectural level.

Docea Power Announces DATE Highlights: Architectural-Level Power Modeling Demonstrations, Testimonial about Using Aceplorer for Mobile Design; Aceplorer 2.2 adds new library of customizable blocks, UPF 2.0 support

Docea Power announced today that it has joined the Synopsys System-Level Catalyst program to ensure the interoperability of its Aceplorer tool with Synopsys System-Level solutions. The Synopsys System-Level Catalyst program accelerates adoption of system-level design and verification by advancing tool and model interoperability as well as availability of system-level models and services.

Docea Power, the design-for-low-power company that delivers software for power and thermal analysis at the architectural level (ESL), announced today that its Aceplorer software has been selected by the University of Tokyo to model and optimize power consumption for new non-volatile memory (NVM) designs and architectures as part of a Japanese national research project.

CoFluent Design and Docea Power, today announced their collaboration to deliver interoperable solutions to accelerate power exploration and optimization of electronic systems. CoFluent is a leading Electronic System Level (ESL) company that provides system-level modeling and simulation to accelerate innovation in embedded devices. Docea is a design-for-low-power company that delivers software for power and thermal analysis at the architectural le...

Docea Power SAS, announces it secured $1.5M in VC money after the successful launch of its Aceplorer product in 2009. The funds, raised from Rhône-Alpes Création, Alps Development Sustainable Investment, Siparex, Octalfa, and private investors, will be used to expand the company’s product offering and to increase its commercial deployment abroad, notably in Asia and the United States.

Docea Power, the design-for-low-power company that delivers software solutions for power and thermal analysis at the architectural level, today announced a new version of its system-level power and thermal modeling platform: Aceplorer 2.0. The new version adds project management capabilities to boost productivity and a link to virtual platforms to assess the impact of complex scenarios and embedded software on a system’s power consumption. At t...

Docea Power, the Electronic System Level (ESL) company that delivers software for early power and thermal analysis, today announced that ST-Ericsson, a world leader in wireless platforms and semiconductors, has adopted and is deploying ACEplorer to improve architectural-level power choices for SoC (System-on-Chip) and platform design.